X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=lib%2FTarget%2FMips%2FMSA.txt;h=cc934263287bc33aab0d85e0da0477c4a720d303;hb=211ed6d0017280fe27176338e88a9fee998dc909;hp=270a723048e8bd87e34a5d74ce1e67f932b998b9;hpb=c385709d8397ca1535481c04564b67d07c66c619;p=oota-llvm.git diff --git a/lib/Target/Mips/MSA.txt b/lib/Target/Mips/MSA.txt index 270a723048e..cc934263287 100644 --- a/lib/Target/Mips/MSA.txt +++ b/lib/Target/Mips/MSA.txt @@ -14,6 +14,11 @@ This section describes any quirks of instruction selection for MSA. For example, two instructions might be equally valid for some given IR and one is chosen in preference to the other. +bclri.b: + It is not possible to emit bclri.b since andi.b covers exactly the + same cases. andi.b should use fractionally less power than bclri.b in + most hardware implementations so it is used in preference to bclri.b. + vshf.w: It is not possible to emit vshf.w when the shuffle description is constant since shf.w covers exactly the same cases. shf.w is used @@ -57,11 +62,16 @@ binsri.[bhwd], binsli.[bhwd]: bmnz.v, bmz.v, bsel.v: These three operations differ only in the operand that is tied to the - result. + result and the order of the operands. It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is the same operation and will be emitted instead. In future, the compiler may choose between these three instructions according to register allocation. + These three operations can be very confusing so here is a mapping + between the instructions and the vselect node in one place: + bmz.v wd, ws, wt/i8 -> (vselect wt/i8, wd, ws) + bmnz.v wd, ws, wt/i8 -> (vselect wt/i8, ws, wd) + bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws) bmnzi.b, bmzi.b: Like their non-immediate counterparts, bmnzi.v and bmzi.v are the same @@ -71,3 +81,4 @@ bmnzi.b, bmzi.b: bseli.v: Unlike the non-immediate versions, bseli.v is distinguishable from bmnzi.b and bmzi.b and can be emitted. +