X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fphy%2Fphy-rockchip-inno-usb2.c;h=df92a481402eb68294aec1ca8749dcc1b50e1a7f;hb=adb8d1ce4770b040daefd59ef847064442b9c3a4;hp=85b86110ece5771dec74b9f66f361787e9f92a39;hpb=c490a5aad27d1bd60cced88e0406463e181a4edf;p=firefly-linux-kernel-4.4.55.git diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c index 85b86110ece5..df92a481402e 100644 --- a/drivers/phy/phy-rockchip-inno-usb2.c +++ b/drivers/phy/phy-rockchip-inno-usb2.c @@ -5,7 +5,8 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -29,11 +31,16 @@ #include #include #include +#include #include #include +#include +#include +#include #define BIT_WRITEABLE_SHIFT 16 -#define SCHEDULE_DELAY (60 * HZ) +#define SCHEDULE_DELAY (60 * HZ) +#define OTG_SCHEDULE_DELAY (2 * HZ) struct rockchip_usb2phy; @@ -46,8 +53,40 @@ enum rockchip_usb2phy_port_id { enum rockchip_usb2phy_host_state { PHY_STATE_HS_ONLINE = 0, PHY_STATE_DISCONNECT = 1, - PHY_STATE_HS_CONNECT = 2, - PHY_STATE_FS_CONNECT = 4, + PHY_STATE_CONNECT = 2, + PHY_STATE_FS_LS_ONLINE = 4, +}; + +/** + * Different states involved in USB charger detection. + * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection + * process is not yet started. + * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact. + * USB_CHG_STATE_DCD_DONE Data pin contact is detected. + * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects + * between SDP and DCP/CDP). + * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects + * between DCP and CDP). + * USB_CHG_STATE_DETECTED USB charger type is determined. + */ +enum usb_chg_state { + USB_CHG_STATE_UNDEFINED = 0, + USB_CHG_STATE_WAIT_FOR_DCD, + USB_CHG_STATE_DCD_DONE, + USB_CHG_STATE_PRIMARY_DONE, + USB_CHG_STATE_SECONDARY_DONE, + USB_CHG_STATE_DETECTED, +}; + +static const unsigned int rockchip_usb2phy_extcon_cable[] = { + EXTCON_USB, + EXTCON_USB_HOST, + EXTCON_USB_VBUS_EN, + EXTCON_CHG_USB_SDP, + EXTCON_CHG_USB_CDP, + EXTCON_CHG_USB_DCP, + EXTCON_CHG_USB_SLOW, + EXTCON_NONE, }; struct usb2phy_reg { @@ -58,77 +97,170 @@ struct usb2phy_reg { unsigned int enable; }; +/** + * struct rockchip_chg_det_reg: usb charger detect registers + * @cp_det: charging port detected successfully. + * @dcp_det: dedicated charging port detected successfully. + * @dp_det: assert data pin connect successfully. + * @idm_sink_en: open dm sink curren. + * @idp_sink_en: open dp sink current. + * @idp_src_en: open dm source current. + * @rdm_pdwn_en: open dm pull down resistor. + * @vdm_src_en: open dm voltage source. + * @vdp_src_en: open dp voltage source. + * @opmode: utmi operational mode. + */ +struct rockchip_chg_det_reg { + struct usb2phy_reg cp_det; + struct usb2phy_reg dcp_det; + struct usb2phy_reg dp_det; + struct usb2phy_reg idm_sink_en; + struct usb2phy_reg idp_sink_en; + struct usb2phy_reg idp_src_en; + struct usb2phy_reg rdm_pdwn_en; + struct usb2phy_reg vdm_src_en; + struct usb2phy_reg vdp_src_en; + struct usb2phy_reg opmode; +}; + /** * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. * @phy_sus: phy suspend register. + * @bvalid_det_en: vbus valid rise detection enable register. + * @bvalid_det_st: vbus valid rise detection status register. + * @bvalid_det_clr: vbus valid rise detection clear register. * @ls_det_en: linestate detection enable register. * @ls_det_st: linestate detection state register. * @ls_det_clr: linestate detection clear register. + * @idfall_det_en: id fall detection enable register. + * @idfall_det_st: id fall detection state register. + * @idfall_det_clr: id fall detection clear register. + * @idrise_det_en: id rise detection enable register. + * @idrise_det_st: id rise detection state register. + * @idrise_det_clr: id rise detection clear register. + * @utmi_avalid: utmi vbus avalid status register. + * @utmi_bvalid: utmi vbus bvalid status register. + * @utmi_iddig: otg port id pin status register. * @utmi_ls: utmi linestate state register. * @utmi_hstdet: utmi host disconnect register. */ struct rockchip_usb2phy_port_cfg { struct usb2phy_reg phy_sus; + struct usb2phy_reg bvalid_det_en; + struct usb2phy_reg bvalid_det_st; + struct usb2phy_reg bvalid_det_clr; struct usb2phy_reg ls_det_en; struct usb2phy_reg ls_det_st; struct usb2phy_reg ls_det_clr; + struct usb2phy_reg idfall_det_en; + struct usb2phy_reg idfall_det_st; + struct usb2phy_reg idfall_det_clr; + struct usb2phy_reg idrise_det_en; + struct usb2phy_reg idrise_det_st; + struct usb2phy_reg idrise_det_clr; + struct usb2phy_reg utmi_avalid; + struct usb2phy_reg utmi_bvalid; + struct usb2phy_reg utmi_iddig; struct usb2phy_reg utmi_ls; struct usb2phy_reg utmi_hstdet; }; /** * struct rockchip_usb2phy_cfg: usb-phy configuration. + * @reg: the address offset of grf for usb-phy config. * @num_ports: specify how many ports that the phy has. * @phy_tuning: phy default parameters tunning. * @clkout_ctl: keep on/turn off output clk of phy. + * @chg_det: charger detection registers. */ struct rockchip_usb2phy_cfg { + unsigned int reg; unsigned int num_ports; int (*phy_tuning)(struct rockchip_usb2phy *); struct usb2phy_reg clkout_ctl; - const struct rockchip_usb2phy_port_cfg *port_cfgs; + const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; + const struct rockchip_chg_det_reg chg_det; }; /** * struct rockchip_usb2phy_port: usb-phy port data. * @port_id: flag for otg port or host port. + * @perip_connected: flag for periphyeral connect status. * @suspended: phy suspended flag. + * @utmi_avalid: utmi avalid status usage flag. + * true - use avalid to get vbus status + * flase - use bvalid to get vbus status + * @vbus_attached: otg device vbus status. + * @vbus_always_on: otg vbus is always powered on. + * @bvalid_irq: IRQ number assigned for vbus valid rise detection. * @ls_irq: IRQ number assigned for linestate detection. + * @id_irq: IRQ number assigned for id fall or rise detection. * @mutex: for register updating in sm_work. - * @sm_work: OTG state machine work. + * @chg_work: charge detect work. + * @otg_sm_work: OTG state machine work. + * @sm_work: HOST state machine work. * @phy_cfg: port register configuration, assigned by driver data. + * @event_nb: hold event notification callback. + * @wakelock: wake lock struct to prevent system suspend + * when USB is active. + * @state: define OTG enumeration states before device reset. + * @mode: the dr_mode of the controller. */ struct rockchip_usb2phy_port { struct phy *phy; unsigned int port_id; + bool perip_connected; bool suspended; + bool utmi_avalid; + bool vbus_attached; + bool vbus_always_on; + int bvalid_irq; int ls_irq; + int id_irq; struct mutex mutex; + struct delayed_work chg_work; + struct delayed_work otg_sm_work; struct delayed_work sm_work; const struct rockchip_usb2phy_port_cfg *port_cfg; + struct notifier_block event_nb; + struct wake_lock wakelock; + enum usb_otg_state state; + enum usb_dr_mode mode; }; /** * struct rockchip_usb2phy: usb2.0 phy driver data. * @grf: General Register Files regmap. + * @clk: clock struct of phy input clk. * @clk480m: clock struct of phy output clk. * @clk_hw: clock struct of phy output clk management. - * @vbus_host_gpio: host VBUS direction output. + * @chg_state: states involved in USB charger detection. + * @chg_type: USB charger types. + * @dcd_retries: The retry count used to track Data contact + * detection process. + * @edev_self: represent the source of extcon. + * @edev: extcon device for notification registration * @phy_cfg: phy register configuration, assigned by driver data. * @ports: phy port instance. */ struct rockchip_usb2phy { struct device *dev; struct regmap *grf; + struct clk *clk; struct clk *clk480m; struct clk_hw clk480m_hw; - struct gpio_desc *vbus_host_gpio; + enum usb_chg_state chg_state; + enum power_supply_type chg_type; + u8 dcd_retries; + u8 primary_retries; + bool edev_self; + struct extcon_dev *edev; const struct rockchip_usb2phy_cfg *phy_cfg; struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; }; static inline int property_enable(struct rockchip_usb2phy *rphy, - const struct usb2phy_reg *reg, bool en) + const struct usb2phy_reg *reg, bool en) { unsigned int val, mask, tmp; @@ -158,7 +290,7 @@ static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); - int ret = 0; + int ret; /* turn on 480m clk output if it is off */ if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) { @@ -167,22 +299,16 @@ static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw) return ret; /* waitting for the clk become stable */ - mdelay(1); + udelay(1200); } - return ret; + return 0; } static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); - int index; - - /* make sure all ports in suspended mode */ - for (index = 0; index != rphy->phy_cfg->num_ports; index++) - if (!rphy->ports[index].suspended) - return; /* turn off 480m clk output */ property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false); @@ -210,29 +336,99 @@ static const struct clk_ops rockchip_usb2phy_clkout_ops = { .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, }; -static struct clk * +static void rockchip_usb2phy_clk480m_unregister(void *data) +{ + struct rockchip_usb2phy *rphy = data; + + of_clk_del_provider(rphy->dev->of_node); + clk_unregister(rphy->clk480m); +} + +static int rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) { struct device_node *node = rphy->dev->of_node; - struct clk *clk; struct clk_init_data init; + const char *clk_name; + int ret; + init.flags = 0; init.name = "clk_usbphy_480m"; init.ops = &rockchip_usb2phy_clkout_ops; - init.flags = CLK_IS_ROOT; - init.parent_names = NULL; - init.num_parents = 0; - rphy->clk480m_hw.init = &init; /* optional override of the clockname */ of_property_read_string(node, "clock-output-names", &init.name); + if (rphy->clk) { + clk_name = __clk_get_name(rphy->clk); + init.parent_names = &clk_name; + init.num_parents = 1; + } else { + init.parent_names = NULL; + init.num_parents = 0; + } + + rphy->clk480m_hw.init = &init; + /* register the clock */ - clk = clk_register(rphy->dev, &rphy->clk480m_hw); - if (!IS_ERR(clk)) - of_clk_add_provider(node, of_clk_src_simple_get, clk); + rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); + if (IS_ERR(rphy->clk480m)) { + ret = PTR_ERR(rphy->clk480m); + goto err_ret; + } - return clk; + ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); + if (ret < 0) + goto err_clk_provider; + + ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister, + rphy); + if (ret < 0) + goto err_unreg_action; + + return 0; + +err_unreg_action: + of_clk_del_provider(node); +err_clk_provider: + clk_unregister(rphy->clk480m); +err_ret: + return ret; +} + +static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) +{ + int ret; + struct device_node *node = rphy->dev->of_node; + struct extcon_dev *edev; + + if (of_property_read_bool(node, "extcon")) { + edev = extcon_get_edev_by_phandle(rphy->dev, 0); + if (IS_ERR(edev)) { + if (PTR_ERR(edev) != -EPROBE_DEFER) + dev_err(rphy->dev, "Invalid or missing extcon\n"); + return PTR_ERR(edev); + } + } else { + /* Initialize extcon device */ + edev = devm_extcon_dev_allocate(rphy->dev, + rockchip_usb2phy_extcon_cable); + + if (IS_ERR(edev)) + return -ENOMEM; + + ret = devm_extcon_dev_register(rphy->dev, edev); + if (ret) { + dev_err(rphy->dev, "failed to register extcon device\n"); + return ret; + } + + rphy->edev_self = true; + } + + rphy->edev = edev; + + return 0; } static int rockchip_usb2phy_init(struct phy *phy) @@ -241,36 +437,90 @@ static int rockchip_usb2phy_init(struct phy *phy) struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); int ret = 0; - if (rport->port_id == USB2PHY_PORT_HOST) { - /* clear linestate and enable linestate detect irq */ - mutex_lock(&rport->mutex); + mutex_lock(&rport->mutex); - ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true); - if (ret) { - mutex_unlock(&rport->mutex); - return ret; + if (rport->port_id == USB2PHY_PORT_OTG) { + if (rport->mode != USB_DR_MODE_HOST && + !rport->vbus_always_on) { + /* clear bvalid status and enable bvalid detect irq */ + ret = property_enable(rphy, + &rport->port_cfg-> + bvalid_det_clr, + true); + if (ret) + goto out; + + ret = property_enable(rphy, + &rport->port_cfg-> + bvalid_det_en, + true); + if (ret) + goto out; + + if (rphy->edev_self) { + ret = property_enable(rphy, + &rport->port_cfg-> + idfall_det_clr, + true); + if (ret) + goto out; + + ret = property_enable(rphy, + &rport->port_cfg-> + idfall_det_en, + true); + if (ret) + goto out; + + ret = property_enable(rphy, + &rport->port_cfg-> + idrise_det_clr, + true); + if (ret) + goto out; + + ret = property_enable(rphy, + &rport->port_cfg-> + idrise_det_en, + true); + if (ret) + goto out; + } + + schedule_delayed_work(&rport->otg_sm_work, + OTG_SCHEDULE_DELAY); + } else { + /* If OTG works in host only mode, do nothing. */ + dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); } + } else if (rport->port_id == USB2PHY_PORT_HOST) { + /* clear linestate and enable linestate detect irq */ + ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true); + if (ret) + goto out; ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true); - if (ret) { - mutex_unlock(&rport->mutex); - return ret; - } + if (ret) + goto out; - mutex_unlock(&rport->mutex); schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); } +out: + mutex_unlock(&rport->mutex); return ret; } -static int rockchip_usb2phy_resume(struct phy *phy) +static int rockchip_usb2phy_power_on(struct phy *phy) { struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); int ret; - dev_dbg(&rport->phy->dev, "port resume\n"); + dev_dbg(&rport->phy->dev, "port power on\n"); + + if (!rport->suspended) + return 0; ret = clk_prepare_enable(rphy->clk480m); if (ret) @@ -284,13 +534,16 @@ static int rockchip_usb2phy_resume(struct phy *phy) return 0; } -static int rockchip_usb2phy_suspend(struct phy *phy) +static int rockchip_usb2phy_power_off(struct phy *phy) { struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); int ret; - dev_dbg(&rport->phy->dev, "port suspend\n"); + dev_dbg(&rport->phy->dev, "port power off\n"); + + if (rport->suspended) + return 0; ret = property_enable(rphy, &rport->port_cfg->phy_sus, true); if (ret) @@ -298,6 +551,7 @@ static int rockchip_usb2phy_suspend(struct phy *phy) rport->suspended = true; clk_disable_unprepare(rphy->clk480m); + return 0; } @@ -305,7 +559,11 @@ static int rockchip_usb2phy_exit(struct phy *phy) { struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); - if (rport->port_id == USB2PHY_PORT_HOST) + if (rport->port_id == USB2PHY_PORT_OTG && + rport->mode != USB_DR_MODE_HOST && + !rport->vbus_always_on) + cancel_delayed_work_sync(&rport->chg_work); + else if (rport->port_id == USB2PHY_PORT_HOST) cancel_delayed_work_sync(&rport->sm_work); return 0; @@ -314,23 +572,297 @@ static int rockchip_usb2phy_exit(struct phy *phy) static const struct phy_ops rockchip_usb2phy_ops = { .init = rockchip_usb2phy_init, .exit = rockchip_usb2phy_exit, - .power_on = rockchip_usb2phy_resume, - .power_off = rockchip_usb2phy_suspend, + .power_on = rockchip_usb2phy_power_on, + .power_off = rockchip_usb2phy_power_off, .owner = THIS_MODULE, }; +static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) +{ + struct rockchip_usb2phy_port *rport = + container_of(work, struct rockchip_usb2phy_port, + otg_sm_work.work); + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + static unsigned int cable; + unsigned long delay; + bool sch_work; + + if (rport->utmi_avalid) + rport->vbus_attached = + property_enabled(rphy, &rport->port_cfg->utmi_avalid); + else + rport->vbus_attached = + property_enabled(rphy, &rport->port_cfg->utmi_bvalid); + + sch_work = false; + delay = OTG_SCHEDULE_DELAY; + + dev_dbg(&rport->phy->dev, "%s otg sm work\n", + usb_otg_state_string(rport->state)); + + switch (rport->state) { + case OTG_STATE_UNDEFINED: + rport->state = OTG_STATE_B_IDLE; + if (!rport->vbus_attached) + rockchip_usb2phy_power_off(rport->phy); + /* fall through */ + case OTG_STATE_B_IDLE: + if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 || + extcon_get_cable_state_(rphy->edev, + EXTCON_USB_VBUS_EN) > 0) { + dev_dbg(&rport->phy->dev, "usb otg host connect\n"); + rport->state = OTG_STATE_A_HOST; + rockchip_usb2phy_power_on(rport->phy); + return; + } else if (rport->vbus_attached) { + dev_dbg(&rport->phy->dev, "vbus_attach\n"); + switch (rphy->chg_state) { + case USB_CHG_STATE_UNDEFINED: + schedule_delayed_work(&rport->chg_work, 0); + return; + case USB_CHG_STATE_DETECTED: + switch (rphy->chg_type) { + case POWER_SUPPLY_TYPE_USB: + dev_dbg(&rport->phy->dev, + "sdp cable is connecetd\n"); + wake_lock(&rport->wakelock); + cable = EXTCON_CHG_USB_SDP; + rockchip_usb2phy_power_on(rport->phy); + rport->state = OTG_STATE_B_PERIPHERAL; + rport->perip_connected = true; + sch_work = true; + break; + case POWER_SUPPLY_TYPE_USB_DCP: + dev_dbg(&rport->phy->dev, + "dcp cable is connecetd\n"); + cable = EXTCON_CHG_USB_DCP; + rockchip_usb2phy_power_off(rport->phy); + sch_work = true; + break; + case POWER_SUPPLY_TYPE_USB_CDP: + dev_dbg(&rport->phy->dev, + "cdp cable is connecetd\n"); + wake_lock(&rport->wakelock); + cable = EXTCON_CHG_USB_CDP; + rockchip_usb2phy_power_on(rport->phy); + rport->state = OTG_STATE_B_PERIPHERAL; + rport->perip_connected = true; + sch_work = true; + break; + case POWER_SUPPLY_TYPE_USB_FLOATING: + dev_dbg(&rport->phy->dev, + "floating cable is connecetd\n"); + cable = EXTCON_CHG_USB_DCP; + rockchip_usb2phy_power_off(rport->phy); + sch_work = true; + break; + default: + break; + } + break; + default: + break; + } + } else { + rphy->chg_state = USB_CHG_STATE_UNDEFINED; + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; + } + break; + case OTG_STATE_B_PERIPHERAL: + if (!rport->vbus_attached) { + dev_dbg(&rport->phy->dev, "usb disconnect\n"); + rphy->chg_state = USB_CHG_STATE_UNDEFINED; + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; + rport->state = OTG_STATE_B_IDLE; + rport->perip_connected = false; + delay = 0; + rockchip_usb2phy_power_off(rport->phy); + wake_unlock(&rport->wakelock); + } else { + sch_work = true; + } + break; + case OTG_STATE_A_HOST: + if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) { + dev_dbg(&rport->phy->dev, "usb otg host disconnect\n"); + rport->state = OTG_STATE_B_IDLE; + rockchip_usb2phy_power_off(rport->phy); + } + return; + default: + return; + } + + if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached) + extcon_set_cable_state_(rphy->edev, + cable, rport->vbus_attached); + + if (rphy->edev_self && + (extcon_get_state(rphy->edev, EXTCON_USB) != + rport->perip_connected)) + extcon_set_cable_state_(rphy->edev, + EXTCON_USB, + rport->perip_connected); + + if (sch_work) + schedule_delayed_work(&rport->otg_sm_work, delay); +} + +static const char *chg_to_string(enum power_supply_type chg_type) +{ + switch (chg_type) { + case POWER_SUPPLY_TYPE_USB: + return "USB_SDP_CHARGER"; + case POWER_SUPPLY_TYPE_USB_DCP: + return "USB_DCP_CHARGER"; + case POWER_SUPPLY_TYPE_USB_CDP: + return "USB_CDP_CHARGER"; + case POWER_SUPPLY_TYPE_USB_FLOATING: + return "USB_FLOATING_CHARGER"; + default: + return "INVALID_CHARGER"; + } +} + +static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, + bool en) +{ + property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); + property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en); +} + +static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, + bool en) +{ + property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en); + property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en); +} + +static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, + bool en) +{ + property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en); + property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en); +} + +#define CHG_DCD_POLL_TIME (100 * HZ / 1000) +#define CHG_DCD_MAX_RETRIES 6 +#define CHG_PRIMARY_DET_TIME (40 * HZ / 1000) +#define CHG_SECONDARY_DET_TIME (40 * HZ / 1000) +static void rockchip_chg_detect_work(struct work_struct *work) +{ + struct rockchip_usb2phy_port *rport = + container_of(work, struct rockchip_usb2phy_port, chg_work.work); + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + bool is_dcd, tmout, vout; + unsigned long delay; + + dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", + rphy->chg_state); + switch (rphy->chg_state) { + case USB_CHG_STATE_UNDEFINED: + if (!rport->suspended) + rockchip_usb2phy_power_off(rport->phy); + /* put the controller in non-driving mode */ + property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false); + /* Start DCD processing stage 1 */ + rockchip_chg_enable_dcd(rphy, true); + rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; + rphy->dcd_retries = 0; + rphy->primary_retries = 0; + delay = CHG_DCD_POLL_TIME; + break; + case USB_CHG_STATE_WAIT_FOR_DCD: + /* get data contact detection status */ + is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det); + tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES; + /* stage 2 */ + if (is_dcd || tmout) { + /* stage 4 */ + /* Turn off DCD circuitry */ + rockchip_chg_enable_dcd(rphy, false); + /* Voltage Source on DP, Probe on DM */ + rockchip_chg_enable_primary_det(rphy, true); + delay = CHG_PRIMARY_DET_TIME; + rphy->chg_state = USB_CHG_STATE_DCD_DONE; + } else { + /* stage 3 */ + delay = CHG_DCD_POLL_TIME; + } + break; + case USB_CHG_STATE_DCD_DONE: + vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det); + rockchip_chg_enable_primary_det(rphy, false); + if (vout) { + /* Voltage Source on DM, Probe on DP */ + rockchip_chg_enable_secondary_det(rphy, true); + delay = CHG_SECONDARY_DET_TIME; + rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE; + } else { + if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) { + /* floating charger found */ + rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; + rphy->chg_state = USB_CHG_STATE_DETECTED; + delay = 0; + } else { + if (rphy->primary_retries < 2) { + /* Turn off DCD circuitry */ + rockchip_chg_enable_dcd(rphy, false); + /* Voltage Source on DP, Probe on DM */ + rockchip_chg_enable_primary_det(rphy, + true); + delay = CHG_PRIMARY_DET_TIME; + rphy->chg_state = + USB_CHG_STATE_DCD_DONE; + rphy->primary_retries++; + /* break USB_CHG_STATE_DCD_DONE */ + break; + } + rphy->chg_type = POWER_SUPPLY_TYPE_USB; + rphy->chg_state = USB_CHG_STATE_DETECTED; + delay = 0; + } + } + break; + case USB_CHG_STATE_PRIMARY_DONE: + vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det); + /* Turn off voltage source */ + rockchip_chg_enable_secondary_det(rphy, false); + if (vout) + rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; + else + rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP; + /* fall through */ + case USB_CHG_STATE_SECONDARY_DONE: + rphy->chg_state = USB_CHG_STATE_DETECTED; + delay = 0; + /* fall through */ + case USB_CHG_STATE_DETECTED: + /* put the controller in normal mode */ + property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true); + rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); + dev_info(&rport->phy->dev, "charger = %s\n", + chg_to_string(rphy->chg_type)); + return; + default: + return; + } + + schedule_delayed_work(&rport->chg_work, delay); +} + /* * The function manage host-phy port state and suspend/resume phy port * to save power. * * we rely on utmi_linestate and utmi_hostdisconnect to identify whether - * FS/HS is disconnect or not. Besides, we do not need care it is FS + * devices is disconnect or not. Besides, we do not need care it is FS/LS * disconnected or HS disconnected, actually, we just only need get the * device is disconnected at last through rearm the delayed work, * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. * - * NOTE: It will invoke some clk related APIs, so do not invoke it from - * interrupt context. + * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke + * some clk related APIs, so do not invoke it from interrupt context directly. */ static void rockchip_usb2phy_sm_work(struct work_struct *work) { @@ -367,28 +899,36 @@ static void rockchip_usb2phy_sm_work(struct work_struct *work) case PHY_STATE_HS_ONLINE: dev_dbg(&rport->phy->dev, "HS online\n"); break; - case PHY_STATE_FS_CONNECT: + case PHY_STATE_FS_LS_ONLINE: /* - * For FS device, the online state share with connect state + * For FS/LS device, the online state share with connect state * from utmi_ls and utmi_hstdet register, so we distinguish * them via suspended flag. + * + * Plus, there are two cases, one is D- Line pull-up, and D+ + * line pull-down, the state is 4; another is D+ line pull-up, + * and D- line pull-down, the state is 2. */ if (!rport->suspended) { - dev_dbg(&rport->phy->dev, "FS online\n"); + /* D- line pull-up, D+ line pull-down */ + dev_dbg(&rport->phy->dev, "FS/LS online\n"); break; } /* fall through */ - case PHY_STATE_HS_CONNECT: + case PHY_STATE_CONNECT: if (rport->suspended) { - dev_dbg(&rport->phy->dev, "HS/FS connected\n"); - rockchip_usb2phy_resume(rport->phy); + dev_dbg(&rport->phy->dev, "Connected\n"); + rockchip_usb2phy_power_on(rport->phy); rport->suspended = false; + } else { + /* D+ line pull-up, D- line pull-down */ + dev_dbg(&rport->phy->dev, "FS/LS online\n"); } break; case PHY_STATE_DISCONNECT: if (!rport->suspended) { - dev_dbg(&rport->phy->dev, "HS/FS disconnected\n"); - rockchip_usb2phy_suspend(rport->phy); + dev_dbg(&rport->phy->dev, "Disconnected\n"); + rockchip_usb2phy_power_off(rport->phy); rport->suspended = true; } @@ -442,13 +982,68 @@ static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data) return IRQ_HANDLED; } +static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) +{ + struct rockchip_usb2phy_port *rport = data; + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + + if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st)) + return IRQ_NONE; + + mutex_lock(&rport->mutex); + + /* clear bvalid detect irq pending status */ + property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true); + + mutex_unlock(&rport->mutex); + + rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); + + return IRQ_HANDLED; +} + +static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data) +{ + struct rockchip_usb2phy_port *rport = data; + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + + if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) && + !property_enabled(rphy, &rport->port_cfg->idrise_det_st)) + return IRQ_NONE; + + mutex_lock(&rport->mutex); + + /* clear id fall or rise detect irq pending status */ + if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) { + property_enable(rphy, &rport->port_cfg->idfall_det_clr, + true); + extcon_set_state(rphy->edev, EXTCON_USB_HOST, true); + extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true); + } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) { + property_enable(rphy, &rport->port_cfg->idrise_det_clr, + true); + extcon_set_state(rphy->edev, EXTCON_USB_HOST, false); + extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false); + } + + extcon_sync(rphy->edev, EXTCON_USB_HOST); + extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN); + + mutex_unlock(&rport->mutex); + + return IRQ_HANDLED; +} + static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, struct device_node *child_np) { - int ret = 0; + int ret; rport->port_id = USB2PHY_PORT_HOST; + rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; + rport->suspended = true; + mutex_init(&rport->mutex); INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); @@ -463,11 +1058,115 @@ static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, IRQF_ONESHOT, "rockchip_usb2phy", rport); if (ret) { - dev_err(rphy->dev, "failed to request irq handle\n"); + dev_err(rphy->dev, "failed to request linestate irq handle\n"); return ret; } - return ret; + return 0; +} + +static int rockchip_otg_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct rockchip_usb2phy_port *rport = + container_of(nb, struct rockchip_usb2phy_port, event_nb); + + schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY); + + return NOTIFY_DONE; +} + +static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, + struct rockchip_usb2phy_port *rport, + struct device_node *child_np) +{ + int ret; + int iddig; + + rport->port_id = USB2PHY_PORT_OTG; + rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; + rport->state = OTG_STATE_UNDEFINED; + + /* + * set suspended flag to true, but actually don't + * put phy in suspend mode, it aims to enable usb + * phy and clock in power_on() called by usb controller + * driver during probe. + */ + rport->suspended = true; + rport->vbus_attached = false; + rport->perip_connected = false; + + mutex_init(&rport->mutex); + + rport->vbus_always_on = + of_property_read_bool(child_np, "rockchip,vbus-always-on"); + + rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); + if (rport->mode == USB_DR_MODE_HOST || rport->vbus_always_on) + return 0; + + wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg"); + INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); + INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); + + rport->utmi_avalid = + of_property_read_bool(child_np, "rockchip,utmi-avalid"); + + rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); + if (rport->bvalid_irq < 0) { + dev_err(rphy->dev, "no vbus valid irq provided\n"); + return rport->bvalid_irq; + } + + ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL, + rockchip_usb2phy_bvalid_irq, + IRQF_ONESHOT, + "rockchip_usb2phy_bvalid", rport); + if (ret) { + dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n"); + return ret; + } + + if (rphy->edev_self) { + rport->id_irq = of_irq_get_byname(child_np, "otg-id"); + if (rport->id_irq < 0) { + dev_err(rphy->dev, "no otg id irq provided\n"); + return rport->id_irq; + } + + ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL, + rockchip_usb2phy_id_irq, + IRQF_ONESHOT, + "rockchip_usb2phy_id", rport); + if (ret) { + dev_err(rphy->dev, "failed to request otg-id irq handle\n"); + return ret; + } + + iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig); + if (!iddig) { + extcon_set_state(rphy->edev, EXTCON_USB, false); + extcon_set_state(rphy->edev, EXTCON_USB_HOST, true); + extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true); + } else { + extcon_set_state(rphy->edev, EXTCON_USB_HOST, false); + extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false); + } + } + + if (!IS_ERR(rphy->edev)) { + rport->event_nb.notifier_call = rockchip_otg_event; + + ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST, + &rport->event_nb); + if (ret < 0) { + dev_err(rphy->dev, "register USB HOST notifier failed\n"); + return ret; + } + } + + return 0; } static int rockchip_usb2phy_probe(struct platform_device *pdev) @@ -477,7 +1176,9 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) struct device_node *child_np; struct phy_provider *provider; struct rockchip_usb2phy *rphy; + const struct rockchip_usb2phy_cfg *phy_cfgs; const struct of_device_id *match; + unsigned int reg; int index, ret; rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL); @@ -491,38 +1192,76 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) } if (!dev->parent || !dev->parent->of_node) - return -ENOMEM; + return -EINVAL; rphy->grf = syscon_node_to_regmap(dev->parent->of_node); if (IS_ERR(rphy->grf)) return PTR_ERR(rphy->grf); + if (of_property_read_u32(np, "reg", ®)) { + dev_err(dev, "the reg property is not assigned in %s node\n", + np->name); + return -EINVAL; + } + rphy->dev = dev; - rphy->phy_cfg = match->data; + phy_cfgs = match->data; + rphy->chg_state = USB_CHG_STATE_UNDEFINED; + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; + rphy->edev_self = false; platform_set_drvdata(pdev, rphy); - rphy->clk480m = rockchip_usb2phy_clk480m_register(rphy); - if (IS_ERR(rphy->clk480m)) - return PTR_ERR(rphy->clk480m); + ret = rockchip_usb2phy_extcon_register(rphy); + if (ret) + return ret; + + /* find out a proper config which can be matched with dt. */ + index = 0; + while (phy_cfgs[index].reg) { + if (phy_cfgs[index].reg == reg) { + rphy->phy_cfg = &phy_cfgs[index]; + break; + } + + ++index; + } + + if (!rphy->phy_cfg) { + dev_err(dev, "no phy-config can be matched with %s node\n", + np->name); + return -EINVAL; + } + + rphy->clk = of_clk_get_by_name(np, "phyclk"); + if (!IS_ERR(rphy->clk)) { + clk_prepare_enable(rphy->clk); + } else { + dev_info(&pdev->dev, "no phyclk specified\n"); + rphy->clk = NULL; + } + + ret = rockchip_usb2phy_clk480m_register(rphy); + if (ret) { + dev_err(dev, "failed to register 480m output clock\n"); + goto disable_clks; + } if (rphy->phy_cfg->phy_tuning) { ret = rphy->phy_cfg->phy_tuning(rphy); if (ret) - return ret; + goto disable_clks; } - rphy->vbus_host_gpio = - devm_gpiod_get_optional(dev, "vbus_host", GPIOD_OUT_HIGH); - if (!rphy->vbus_host_gpio) - dev_info(dev, "host_vbus is not assigned!\n"); - else if (IS_ERR(rphy->vbus_host_gpio)) - return PTR_ERR(rphy->vbus_host_gpio); - index = 0; - for_each_child_of_node(np, child_np) { + for_each_available_child_of_node(np, child_np) { struct rockchip_usb2phy_port *rport = &rphy->ports[index]; struct phy *phy; + /* This driver aims to support both otg-port and host-port */ + if (of_node_cmp(child_np->name, "host-port") && + of_node_cmp(child_np->name, "otg-port")) + goto next_child; + phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); if (IS_ERR(phy)) { dev_err(dev, "failed to create phy\n"); @@ -531,7 +1270,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) } rport->phy = phy; - rport->port_cfg = &rphy->phy_cfg->port_cfgs[index]; + phy_set_drvdata(rport->phy, rport); /* initialize otg/host port separately */ if (!of_node_cmp(child_np->name, "host-port")) { @@ -539,10 +1278,17 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) child_np); if (ret) goto put_child; + } else { + ret = rockchip_usb2phy_otg_port_init(rphy, rport, + child_np); + if (ret) + goto put_child; } - phy_set_drvdata(rport->phy, rport); - index++; +next_child: + /* to prevent out of boundary */ + if (++index >= rphy->phy_cfg->num_ports) + break; } provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); @@ -550,8 +1296,11 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) put_child: of_node_put(child_np); - of_clk_del_provider(np); - clk_unregister(rphy->clk480m); +disable_clks: + if (rphy->clk) { + clk_disable_unprepare(rphy->clk); + clk_put(rphy->clk); + } return ret; } @@ -574,25 +1323,105 @@ static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy) return ret; } -static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs = { - .num_ports = 1, - .phy_tuning = rk3366_usb2phy_tuning, - .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, - .port_cfgs = (struct rockchip_usb2phy_port_cfg[]) { - { - .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 }, - .ls_det_en = { 0x0680, 4, 4, 0, 1 }, - .ls_det_st = { 0x0690, 4, 4, 0, 1 }, - .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, - .utmi_ls = { 0x049c, 14, 13, 0, 1 }, - .utmi_hstdet = { 0x049c, 12, 12, 0, 1 } +static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = { + { + .reg = 0x700, + .num_ports = 2, + .phy_tuning = rk3366_usb2phy_tuning, + .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, + .utmi_ls = { 0x049c, 14, 13, 0, 1 }, + .utmi_hstdet = { 0x049c, 12, 12, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { + { + .reg = 0xe450, + .num_ports = 2, + .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 }, + .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, + .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, + .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, + .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, + .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, + .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, + .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, + .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, + .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, + .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, + .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, + .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0xe454, 3, 0, 5, 1 }, + .cp_det = { 0xe2ac, 2, 2, 0, 1 }, + .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, + .dp_det = { 0xe2ac, 0, 0, 0, 1 }, + .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, + .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, + .idp_src_en = { 0xe450, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, + .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, + .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0xe460, + .num_ports = 2, + .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 }, + .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, + .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, + .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, + .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, + .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, + .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, + .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, + .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, + .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, + .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, + .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, + .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } + } }, - { /* sentinel */ } }, + { /* sentinel */ } }; static const struct of_device_id rockchip_usb2phy_dt_match[] = { { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, + { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, {} }; MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);