X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3366.dtsi;h=b9a371940240885d838ff84572d1afadba142b44;hb=d356b80cab42a2acb515bc08a1fcc99466627a83;hp=91aa38dcd8eb2678156b0a1ecd5522b793a10c4f;hpb=c7ec32bfff854f1f1bb52ad1d83ba6f1334d8ec8;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi index 91aa38dcd8eb..b9a371940240 100644 --- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi @@ -46,8 +46,10 @@ #include #include #include +#include #include -#include +#include +#include / { compatible = "rockchip,rk3366"; @@ -78,6 +80,11 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&cpu_sleep>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <166>; }; cpu1: cpu@1 { @@ -85,6 +92,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&cpu_sleep>; }; cpu2: cpu@2 { @@ -92,6 +101,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&cpu_sleep>; }; cpu3: cpu@3 { @@ -99,6 +110,66 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&cpu_sleep>; + }; + + idle-states { + entry-method = "psci"; + cpu_sleep: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <350>; + exit-latency-us = <600>; + min-residency-us = <1150>; + }; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1075000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1175000>; + }; + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1250000>; + }; + }; + + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <950000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; }; }; @@ -115,6 +186,18 @@ ; }; + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + xin24m: xin24m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -182,6 +265,82 @@ status = "disabled"; }; + scr: rkscr@ff1d0000 { + compatible = "rockchip-scr"; + reg = <0x0 0xff1d0000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>; + clocks = <&cru PCLK_SIM>; + clock-names = "g_pclk_sim_card"; + status = "disabled"; + }; + + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <1600>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point@0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + target: trip-point@1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@ff260000 { + compatible = "rockchip,rk3366-tsadc"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&tsadc_gpio>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + sdmmc: rksdmmc@ff400000 { compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 150000000>; @@ -225,7 +384,7 @@ interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; clock-names = "stmmaceth", "mac_clk_rx", @@ -330,6 +489,28 @@ status = "disabled"; }; + usb_host0_ehci: usb@ff480000 { + compatible = "generic-ehci"; + reg = <0x0 0xff480000 0x0 0x20000>; + interrupts = ; + clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>; + clock-names = "usbphy_480m", "hclk_host0"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff4a0000 { + compatible = "generic-ohci"; + reg = <0x0 0xff4a0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>; + clock-names = "usbphy_480m", "hclk_host0"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + usb_otg: usb@ff4c0000 { compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", "snps,dwc2"; @@ -358,6 +539,29 @@ status = "disabled"; }; + efuse: efuse@ff670000 { + compatible = "rockchip,rk3366-efuse"; + reg = <0x0 0xff670000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE_256>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpu_leakage: cpu-leakage { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage { + reg = <0x18 0x1>; + }; + logic_leakage: logic-leakage { + reg = <0x19 0x1>; + }; + wafer_info: wafer-info { + reg = <0x1c 0x1>; + }; + }; + pwm0: pwm@ff680000 { compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff680000 0x0 0x10>; @@ -527,7 +731,14 @@ mode-normal = ; mode-recovery = ; mode-fastboot = ; - mode-loader = ; + mode-loader = ; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3366-pmu-pvtm"; + clocks = <&cru SCLK_PVTM_PMU>; + clock-names = "pmu"; + status = "disabled"; }; }; @@ -545,6 +756,7 @@ #dma-cells = <1>; clocks = <&cru ACLK_DMAC_PERI>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; dmac_bus: dma-controller@ff600000 { @@ -555,6 +767,7 @@ #dma-cells = <1>; clocks = <&cru ACLK_DMAC_BUS>; clock-names = "apb_pclk"; + peripherals-req-type-burst; }; }; @@ -565,22 +778,85 @@ #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = + <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>, + <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>, + <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>, + <&cru SCLK_SPDIF_8CH_SRC>, <&cru PLL_CPLL>, <&cru PLL_GPLL>, <&cru PLL_NPLL>, <&cru PLL_MPLL>, <&cru PLL_WPLL>, <&cru PLL_BPLL>, <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>, - <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>; + <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>, + <&cru ACLK_BUS>, <&cru ACLK_PERI0>, + <&cru ACLK_PERI1>; assigned-clock-rates = + <0>, <0>, + <0>, <0>, + <0>, <0>, + <0>, <750000000>, <576000000>, <594000000>, <594000000>, - <480000000>, <520000000>, + <960000000>, <520000000>, <375000000>, <288000000>, - <100000000>, <100000000>; + <100000000>, <100000000>, + <288000000>, <288000000>, + <144000000>; + assigned-clock-parents = + <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>, + <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>, + <&cru PLL_GPLL>, <&cru PLL_GPLL>, + <&cru PLL_GPLL>; }; grf: syscon@ff770000 { - compatible = "rockchip,rk3366-grf", "syscon"; + compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@700 { + compatible = "rockchip,rk3366-usb2phy"; + reg = <0x700 0x2c>; + clocks = <&cru SCLK_OTG_PHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "sclk_otgphy0_480m"; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "okay"; + }; + }; + + pvtm: pvtm { + compatible = "rockchip,rk3366-pvtm"; + clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>; + clock-names = "core", "gpu"; + status = "disabled"; + }; + }; + + wdt: watchdog@ff800000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + spdif: spdif@ff880000 { + compatible = "rockchip,rk3366-spdif"; + reg = <0x0 0xff880000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac_bus 3>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_bus>; + status = "disabled"; }; i2s_2ch: i2s-2ch@ff890000 { @@ -589,8 +865,8 @@ interrupts = ; dmas = <&dmac_bus 6>, <&dmac_bus 7>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; status = "disabled"; }; @@ -600,8 +876,8 @@ interrupts = ; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s_8ch_bus>; status = "disabled"; @@ -641,6 +917,17 @@ status = "disabled"; }; + iep: iep@ff900000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + reg = <0x0 0xff900000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + version = <2>; + status = "disabled"; + }; + rga: rga@ff920000 { compatible = "rockchip,rga2"; dev_mode = <1>; @@ -675,8 +962,36 @@ status = "disabled"; }; + iep_mmu: iep-mmu { + dbgname = "iep"; + compatible = "rockchip,iep_mmu"; + reg = <0x0 0xff900800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + status = "disabled"; + }; + + vpu_mmu: vpu_mmu { + dbgname = "vpu"; + compatible = "rockchip,vpu_mmu"; + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = ; + interrupt-names = "vpu_mmu"; + status = "disabled"; + }; + + vdec_mmu: vdec_mmu { + dbgname = "vdec"; + compatible = "rockchip,vdec_mmu"; + reg = <0x0 0xff9b0480 0x0 0x40>, + <0x0 0xff9b04c0 0x0 0x40>; + interrupts = ; + interrupt-names = "vdec_mmu"; + status = "disabled"; + }; + dsihost0: mipi@ff960000 { - compatible = "rockchip,rk3368-dsi"; + compatible = "rockchip,rk3366-dsi"; rockchip,prop = <0>; reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>; reg-names = "mipi_dsi_host" ,"mipi_dsi_phy"; @@ -717,6 +1032,39 @@ status = "disabled"; }; + vpu: vpu_service@ff9a0000 { + compatible = "rockchip,vpu_service"; + rockchip,grf = <&grf>; + iommu_enabled = <1>; + reg = <0x0 0xff9a0000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "irq_dec", "irq_enc"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>; + reset-names = "video_h", "video_a"; + name = "vpu_service"; + dev_mode = <0>; + status = "disabled"; + }; + + rkvdec: rkvdec@ff9b0000 { + compatible = "rockchip,rkvdec"; + rockchip,grf = <&grf>; + iommu_enabled = <1>; + reg = <0x0 0xff9b0000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core"; + resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>; + reset-names = "video_h", "video_a"; + dev_mode = <2>; + name = "rkvdec"; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3366-pinctrl"; rockchip,grf = <&grf>; @@ -961,6 +1309,12 @@ <5 15 RK_FUNC_2 &pcfg_pull_none>, <5 16 RK_FUNC_2 &pcfg_pull_none>; }; + + i2c2_gpio: i2c2-gpio { + rockchip,pins = + <5 15 RK_FUNC_GPIO &pcfg_pull_none>, + <5 16 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; i2c3 { @@ -977,6 +1331,12 @@ <5 8 RK_FUNC_1 &pcfg_pull_none>, <5 9 RK_FUNC_1 &pcfg_pull_none>; }; + + i2c4_gpio: i2c4-gpio { + rockchip,pins = + <5 8 RK_FUNC_GPIO &pcfg_pull_none>, + <5 9 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; i2c5 { @@ -1007,6 +1367,13 @@ }; }; + spdif { + spdif_bus: spdif-bus { + rockchip,pins = + <5 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + spi0 { spi0_clk: spi0-clk { rockchip,pins = @@ -1049,6 +1416,28 @@ }; }; + scr { + scr_clk: scr-clk { + rockchip,pins = + <5 8 RK_FUNC_2 &pcfg_pull_none>; + }; + + scr_io: scr-io { + rockchip,pins = + <5 9 RK_FUNC_2 &pcfg_pull_up>; + }; + + scr_rst: scr-rst { + rockchip,pins = + <5 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + scr_detect: scr-detect { + rockchip,pins = + <5 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = @@ -1215,17 +1604,19 @@ /* mac_rxd2 */ <2 6 RK_FUNC_1 &pcfg_pull_none>, /* mac_txd3 */ - <2 5 RK_FUNC_1 &pcfg_pull_none>, + <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>, /* mac_txd2 */ - <2 4 RK_FUNC_1 &pcfg_pull_none>, + <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>, /* mac_rxd1 */ <2 3 RK_FUNC_1 &pcfg_pull_none>, /* mac_rxd0 */ <2 2 RK_FUNC_1 &pcfg_pull_none>, /* mac_txd1 */ - <2 1 RK_FUNC_1 &pcfg_pull_none>, + <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>, /* mac_txd0 */ <2 0 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txclkout */ + <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>, /* mac_crs */ /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */ /* mac_rxclkin */ @@ -1233,7 +1624,7 @@ /* mac_mdio */ <2 13 RK_FUNC_1 &pcfg_pull_none>, /* mac_txen */ - <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>, /* mac_clk */ <2 11 RK_FUNC_1 &pcfg_pull_none>, /* mac_rxer */ @@ -1276,8 +1667,84 @@ eth_phy { eth_phy_pwr: eth-phy-pwr { rockchip,pins = - <0 24 RK_FUNC_GPIO &pcfg_pull_none>; + <0 25 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tsadc_pin { + tsadc_gpio: tsadc-gpio { + rockchip,pins = + <0 22 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tsadc_int: tsadc-int { + rockchip,pins = + <0 22 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <0 16 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + }; + + gpu: gpu@ffa30000 { + compatible = "arm,malit764", + "arm,malit76x", + "arm,malit7xx", + "arm,mali-midgard"; + + reg = <0x0 0xffa30000 0 0x10000>; + + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + #cooling-cells = <2>; /* min followed by max */ + operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + + power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <900>; + frequency = <500>; + static-power = <300>; + dynamic-power = <1780>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; + }; + + gpu_opp_table: gpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@96000000 { + opp-hz = /bits/ 64 <96000000>; + opp-microvolt = <1100000>; + }; + opp@192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <1100000>; + }; + opp@288000000 { + opp-hz = /bits/ 64 <288000000>; + opp-microvolt = <1100000>; + }; + opp@375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <1125000>; + }; + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1200000>; + }; }; };