-//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
+//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
-
#include "CodeGenDAGPatterns.h"
#include "CodeGenSchedule.h"
#include "CodeGenTarget.h"
#include <cstdio>
#include <map>
#include <vector>
+
using namespace llvm;
namespace {
void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
};
-} // End anonymous namespace
+} // end anonymous namespace
static void PrintDefList(const std::vector<Record*> &Uses,
unsigned Num, raw_ostream &OS) {
- OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
+ OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
OS << getQualifiedName(Uses[i]) << ", ";
OS << "0 };\n";
Res += "|(1<<MCOI::OptionalDef)";
// Fill in operand type.
- Res += ", MCOI::";
+ Res += ", ";
assert(!Op.OperandType.empty() && "Invalid operand type.");
Res += Op.OperandType;
}
}
-
/// Initialize data structures for generating operand name mappings.
///
/// \param Operands [out] A map used to generate the OpName enum with operand
OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
- OS << "namespace llvm {";
+ OS << "namespace llvm {\n";
OS << "namespace " << Namespace << " {\n";
OS << "namespace " << OpNameNS << " { \n";
OS << "enum {\n";
OS << "OPERAND_LAST";
OS << "\n};\n";
- OS << "} // End namespace OpName\n";
- OS << "} // End namespace " << Namespace << "\n";
- OS << "} // End namespace llvm\n";
+ OS << "} // end namespace OpName\n";
+ OS << "} // end namespace " << Namespace << "\n";
+ OS << "} // end namespace llvm\n";
OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n";
OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
- OS << "namespace llvm {";
+ OS << "namespace llvm {\n";
OS << "namespace " << Namespace << " {\n";
OS << "LLVM_READONLY\n";
OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
OS << " return -1;\n";
}
OS << "}\n";
- OS << "} // End namespace " << Namespace << "\n";
- OS << "} // End namespace llvm\n";
+ OS << "} // end namespace " << Namespace << "\n";
+ OS << "} // end namespace llvm\n";
OS << "#endif //GET_INSTRINFO_NAMED_OPS\n";
}
OS << "\n#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
- OS << "namespace llvm {";
+ OS << "namespace llvm {\n";
OS << "namespace " << Namespace << " {\n";
OS << "namespace OpTypes { \n";
OS << "enum OperandType {\n";
}
OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
- OS << "} // End namespace OpTypes\n";
- OS << "} // End namespace " << Namespace << "\n";
- OS << "} // End namespace llvm\n";
+ OS << "} // end namespace OpTypes\n";
+ OS << "} // end namespace " << Namespace << "\n";
+ OS << "} // end namespace llvm\n";
OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
}
<< TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
<< NumberedInstructions.size() << ");\n}\n\n";
- OS << "} // End llvm namespace \n";
+ OS << "} // end llvm namespace \n";
OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
std::string ClassName = TargetName + "GenInstrInfo";
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
- << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
- << " virtual ~" << ClassName << "();\n"
+ << " explicit " << ClassName
+ << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);\n"
+ << " ~" << ClassName << "() override {}\n"
<< "};\n";
- OS << "} // End llvm namespace \n";
+ OS << "} // end llvm namespace \n";
OS << "#endif // GET_INSTRINFO_HEADER\n\n";
OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
OS << "extern const char " << TargetName << "InstrNameData[];\n";
- OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
- << " : TargetInstrInfo(SO, DO) {\n"
- << " InitMCInstrInfo(" << TargetName << "Insts, "
- << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
- << NumberedInstructions.size() << ");\n}\n"
- << ClassName << "::~" << ClassName << "() {}\n";
- OS << "} // End llvm namespace \n";
+ OS << ClassName << "::" << ClassName
+ << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode)\n"
+ << " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode) {\n"
+ << " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
+ << "InstrNameIndices, " << TargetName << "InstrNameData, "
+ << NumberedInstructions.size() << ");\n}\n";
+ OS << "} // end llvm namespace \n";
OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
OS << " { ";
OS << Num << ",\t" << MinOperands << ",\t"
<< Inst.Operands.NumDefs << ",\t"
- << SchedModels.getSchedClassIdx(Inst) << ",\t"
- << Inst.TheDef->getValueAsInt("Size") << ",\t0";
-
- // Emit all of the target indepedent flags...
- if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
- if (Inst.isReturn) OS << "|(1<<MCID::Return)";
- if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
- if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
- if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
- if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
- if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
- if (Inst.isSelect) OS << "|(1<<MCID::Select)";
- if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
- if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
- if (Inst.isCall) OS << "|(1<<MCID::Call)";
- if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
- if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
- if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
- if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
- if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
- if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
- if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
- if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
- if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
- if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
- if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
- if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
- if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
- if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
- if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
- if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
- if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
- if (Inst.isRegSequence) OS << "|(1<<MCID::RegSequence)";
+ << Inst.TheDef->getValueAsInt("Size") << ",\t"
+ << SchedModels.getSchedClassIdx(Inst) << ",\t0";
+
+ // Emit all of the target independent flags...
+ if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
+ if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
+ if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)";
+ if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)";
+ if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
+ if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
+ if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
+ if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
+ if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
+ if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
+ if (Inst.isCall) OS << "|(1ULL<<MCID::Call)";
+ if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)";
+ if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)";
+ if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)";
+ if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
+ if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
+ if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
+ if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)";
+ if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
+ if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)";
+ if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
+ if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
+ if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)";
+ if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
+ if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
+ if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
+ if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
+ if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
+ if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
+ if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
+ if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
+ if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
// Emit all of the target-specific flags...
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
CodeGenTarget &Target = CDP.getTargetInfo();
if (Inst.HasComplexDeprecationPredicate)
// Emit a function pointer to the complex predicate method.
- OS << ",0"
+ OS << ", -1 "
<< ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
else if (!Inst.DeprecatedReason.empty())
// Emit the Subtarget feature.
- OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
- << ",nullptr";
+ OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
+ << " ,nullptr";
else
// Instruction isn't deprecated.
- OS << ",0,nullptr";
+ OS << ", -1 ,nullptr";
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
// We must emit the PHI opcode first...
std::string Namespace = Target.getInstNamespace();
- if (Namespace.empty()) {
- fprintf(stderr, "No instructions defined!\n");
- exit(1);
- }
+ if (Namespace.empty())
+ PrintFatalError("No instructions defined!");
const std::vector<const CodeGenInstruction*> &NumberedInstructions =
Target.getInstructionsByEnumValue();
for (const CodeGenInstruction *Inst : NumberedInstructions)
OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
- OS << " };\n";
+ OS << " };\n\n";
OS << "namespace Sched {\n";
OS << " enum {\n";
Num = 0;
for (const auto &Class : SchedModels.explicit_classes())
OS << " " << Class.Name << "\t= " << Num++ << ",\n";
OS << " SCHED_LIST_END = " << SchedModels.numInstrSchedClasses() << "\n";
- OS << " };\n}\n}\n";
- OS << "} // End llvm namespace \n";
+ OS << " };\n";
+ OS << "} // end Sched namespace\n";
+ OS << "} // end " << Namespace << " namespace\n";
+ OS << "} // end llvm namespace \n";
OS << "#endif // GET_INSTRINFO_ENUM\n\n";
}
EmitMapTable(RK, OS);
}
-} // End llvm namespace
+} // end llvm namespace