#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/MachineValueType.h"
struct MaskRolPair {
unsigned Mask;
uint8_t RotateLeft;
- bool operator==(const MaskRolPair Other) {
+ bool operator==(const MaskRolPair Other) const {
return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
}
- bool operator!=(const MaskRolPair Other) {
+ bool operator!=(const MaskRolPair Other) const {
return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
}
};
unsigned EnumValue;
unsigned CostPerUse;
bool CoveredBySubRegs;
+ bool HasDisjunctSubRegs;
// Map SubRegIndex -> Register.
typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
int CopyCost;
bool Allocatable;
std::string AltOrderSelect;
+ uint8_t AllocationPriority;
/// Contains the combination of the lane masks of all subregisters.
unsigned LaneMask;
+ /// True if there are at least 2 subregisters which do not interfere.
+ bool HasDisjunctSubRegs;
// Return the Record that defined this class, or NULL if the class was
// created by TableGen.