Record *R = *I;
if (R->getName() == "PHI" ||
R->getName() == "INLINEASM" ||
- R->getName() == "LABEL" ||
+ R->getName() == "DBG_LABEL" ||
+ R->getName() == "EH_LABEL" ||
+ R->getName() == "GC_LABEL" ||
R->getName() == "DECLARE" ||
R->getName() == "EXTRACT_SUBREG" ||
- R->getName() == "INSERT_SUBREG") continue;
-
+ R->getName() == "INSERT_SUBREG" ||
+ R->getName() == "IMPLICIT_DEF" ||
+ R->getName() == "SUBREG_TO_REG" ||
+ R->getName() == "COPY_TO_REGCLASS") continue;
+
BitsInit *BI = R->getValueAsBitsInit("Inst");
unsigned numBits = BI->getNumBits();
}
-void CodeEmitterGen::run(std::ostream &o) {
+void CodeEmitterGen::run(raw_ostream &o) {
CodeGenTarget Target;
std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
// Emit function declaration
o << "unsigned " << Target.getName() << "CodeEmitter::"
- << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
+ << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
// Emit instruction base values
o << " static const unsigned InstBits[] = {\n";
const CodeGenInstruction *CGI = *IN;
Record *R = CGI->TheDef;
- if (IN != NumberedInstructions.begin()) o << ",\n";
-
if (R->getName() == "PHI" ||
R->getName() == "INLINEASM" ||
- R->getName() == "LABEL" ||
+ R->getName() == "DBG_LABEL" ||
+ R->getName() == "EH_LABEL" ||
+ R->getName() == "GC_LABEL" ||
R->getName() == "DECLARE" ||
R->getName() == "EXTRACT_SUBREG" ||
- R->getName() == "INSERT_SUBREG") {
- o << " 0U";
+ R->getName() == "INSERT_SUBREG" ||
+ R->getName() == "IMPLICIT_DEF" ||
+ R->getName() == "SUBREG_TO_REG" ||
+ R->getName() == "COPY_TO_REGCLASS") {
+ o << " 0U,\n";
continue;
}
Value |= B->getValue() << (e-i-1);
}
}
- o << " " << Value << "U";
+ o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n";
}
- o << "\n };\n";
+ o << " 0U\n };\n";
// Map to accumulate all the cases.
std::map<std::string, std::vector<std::string> > CaseMap;
if (InstName == "PHI" ||
InstName == "INLINEASM" ||
- InstName == "LABEL"||
+ InstName == "DBG_LABEL"||
+ InstName == "EH_LABEL"||
+ InstName == "GC_LABEL"||
InstName == "DECLARE"||
InstName == "EXTRACT_SUBREG" ||
- InstName == "INSERT_SUBREG") continue;
-
+ InstName == "INSERT_SUBREG" ||
+ InstName == "IMPLICIT_DEF" ||
+ InstName == "SUBREG_TO_REG" ||
+ InstName == "COPY_TO_REGCLASS") continue;
+
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();
CodeGenInstruction &CGI = Target.getInstruction(InstName);
gotOp = true;
}
- unsigned opMask = (1 << N) - 1;
+ unsigned opMask = ~0U >> (32-N);
int opShift = beginVarBit - N + 1;
opMask <<= opShift;
opShift = beginInstBit - beginVarBit;
// Emit initial function code
o << " const unsigned opcode = MI.getOpcode();\n"
<< " unsigned Value = InstBits[opcode];\n"
- << " unsigned op;\n"
+ << " unsigned op = 0;\n"
+ << " op = op; // suppress warning\n"
<< " switch (opcode) {\n";
// Emit each case statement
// Default case: unhandled opcode
o << " default:\n"
- << " cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
- << " abort();\n"
+ << " std::string msg;\n"
+ << " raw_string_ostream Msg(msg);\n"
+ << " Msg << \"Not supported instr: \" << MI;\n"
+ << " llvm_report_error(Msg.str());\n"
<< " }\n"
<< " return Value;\n"
<< "}\n\n";