Fix a broadcast related regression on the vector shuffle lowering.

[oota-llvm.git] / test / CodeGen / X86 / vshift-3.ll

diff --git a/test/CodeGen/X86/vshift-3.ll b/test/CodeGen/X86/vshift-3.ll
index b2b48b9da9351de33f61fc07daab5cd8c54a9741..0bdb32fcb86e13638bd5245940e39c319ee65d97 100644 (file)
--- a/test/CodeGen/X86/vshift-3.ll
+++ b/test/CodeGen/X86/vshift-3.ll
@@ -8,7 +8,7 @@
 ; shift1a can't use a packed shift
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: sarl
   %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %ashr, <2 x i64>* %dst
@@ -17,7 +17,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: psrad $5
   %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %ashr, <4 x i32>* %dst
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: psrad
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -40,7 +40,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psraw $5
   %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %ashr, <8 x i16>* %dst
@@ -49,18 +49,18 @@ entry:
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK: psraw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
-  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
-  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
-  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
-  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
-  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
-  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
   %ashr = ashr <8 x i16> %val, %7
   store <8 x i16> %ashr, <8 x i16>* %dst
   ret void