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[AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
[oota-llvm.git]
/
test
/
CodeGen
/
AArch64
/
arm64-arith.ll
diff --git
a/test/CodeGen/AArch64/arm64-arith.ll
b/test/CodeGen/AArch64/arm64-arith.ll
index ed9b569e21821b7cfdcc797c35e18d85ccaec1b0..f36e706b15ddaaef5f51dbe536450da5a2175733 100644
(file)
--- a/
test/CodeGen/AArch64/arm64-arith.ll
+++ b/
test/CodeGen/AArch64/arm64-arith.ll
@@
-260,3
+260,11
@@
define i64 @f3(i64 %a) nounwind readnone ssp {
%res = mul nsw i64 %a, 17
ret i64 %res
}
+
+define i32 @f4(i32 %a) nounwind readnone ssp {
+; CHECK-LABEL: f4:
+; CHECK-NEXT: add w0, w0, w0, lsl #1
+; CHECK-NEXT: ret
+ %res = mul i32 %a, 3
+ ret i32 %res
+}