static int wm8962_reset(struct snd_soc_codec *codec)
{
- int ret;
-
- ret = snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
- if (ret != 0)
- return ret;
-
- return snd_soc_write(codec, WM8962_PLL_SOFTWARE_RESET, 0);
+ return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
}
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ u16 *reg_cache = codec->reg_cache;
int ret;
/* Apply the update (if any) */
return 0;
/* If the left PGA is enabled hit that VU bit... */
- ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
- if (ret & WM8962_SPKOUTL_PGA_ENA) {
- snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
- snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
- return 1;
- }
+ if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
+ return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
+ reg_cache[WM8962_SPKOUTL_VOLUME]);
/* ...otherwise the right. The VU is stereo. */
- if (ret & WM8962_SPKOUTR_PGA_ENA)
- snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
- snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
+ if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
+ return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
+ reg_cache[WM8962_SPKOUTR_VOLUME]);
- return 1;
+ return 0;
}
static const char *cap_hpf_mode_text[] = {
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
+ u16 *reg_cache = codec->reg_cache;
int reg;
switch (w->shift) {
switch (event) {
case SND_SOC_DAPM_POST_PMU:
- return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
+ return snd_soc_write(codec, reg, reg_cache[reg]);
default:
BUG();
return -EINVAL;
}
}
-static const char *st_text[] = { "None", "Left", "Right" };
+static const char *st_text[] = { "None", "Right", "Left" };
static const struct soc_enum str_enum =
SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
/* VMID 2*250k */
snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
WM8962_VMID_SEL_MASK, 0x100);
-
- if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
- msleep(100);
break;
case SND_SOC_BIAS_OFF:
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
- aif0 |= 0x4;
+ aif0 |= 0x40;
break;
case SNDRV_PCM_FORMAT_S24_LE:
- aif0 |= 0x8;
+ aif0 |= 0x80;
break;
case SNDRV_PCM_FORMAT_S32_LE:
- aif0 |= 0xc;
+ aif0 |= 0xc0;
break;
default:
return -EINVAL;
int aif0 = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
- case SND_SOC_DAIFMT_DSP_B:
- aif0 |= WM8962_LRCLK_INV | 3;
case SND_SOC_DAIFMT_DSP_A:
+ aif0 |= WM8962_LRCLK_INV;
+ case SND_SOC_DAIFMT_DSP_B:
aif0 |= 3;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
*/
snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
- /* Ensure that the oscillator and PLLs are disabled */
- snd_soc_update_bits(codec, WM8962_PLL2,
- WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
- 0);
-
regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
if (pdata) {