UPSTREAM: ASoC: da7219: Update PLL ranges and dividers to improve locking

[firefly-linux-kernel-4.4.55.git] / sound / soc / codecs / da7219.c

diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 81c0708b85c1569ad6e109dfac647c732d504b55..3b1d65badbdab9389d274454df415eb05d9bfa5e 100644 (file)
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1079,21 +1079,21 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
                dev_err(codec->dev, "PLL input clock %d below valid range\n",
                        da7219->mclk_rate);
                return -EINVAL;
-       } else if (da7219->mclk_rate <= 5000000) {
-               indiv_bits = DA7219_PLL_INDIV_2_5_MHZ;
-               indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL;
-       } else if (da7219->mclk_rate <= 10000000) {
-               indiv_bits = DA7219_PLL_INDIV_5_10_MHZ;
-               indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL;
-       } else if (da7219->mclk_rate <= 20000000) {
-               indiv_bits = DA7219_PLL_INDIV_10_20_MHZ;
-               indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL;
-       } else if (da7219->mclk_rate <= 40000000) {
-               indiv_bits = DA7219_PLL_INDIV_20_40_MHZ;
-               indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL;
+       } else if (da7219->mclk_rate <= 4500000) {
+               indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
+               indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
+       } else if (da7219->mclk_rate <= 9000000) {
+               indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
+               indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
+       } else if (da7219->mclk_rate <= 18000000) {
+               indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
+               indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
+       } else if (da7219->mclk_rate <= 36000000) {
+               indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
+               indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
        } else if (da7219->mclk_rate <= 54000000) {
-               indiv_bits = DA7219_PLL_INDIV_40_54_MHZ;
-               indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL;
+               indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
+               indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
        } else {
                dev_err(codec->dev, "PLL input clock %d above valid range\n",
                        da7219->mclk_rate);