Fix PR149 - support constant shift expressions.

[oota-llvm.git] / lib / Target / X86 / X86ISelSimple.cpp

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 1242545d83a3a623837920be3d3dde8c4029f675..1616ec1f9821f1ba096753d2d5a0d4d22578f1c4 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -29,6 +29,8 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/InstVisitor.h"
 
+namespace llvm {
+
 /// BMI - A special BuildMI variant that takes an iterator to insert the
 /// instruction at as well as a basic block.  This is the version for when you
 /// have a destination register in mind.
@@ -138,7 +140,7 @@ namespace {
     void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
                 const std::vector<ValueRecord> &Args);
     void visitCallInst(CallInst &I);
-    void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
+    void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
 
     // Arithmetic operators
     void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
@@ -1045,7 +1047,7 @@ void ISel::visitCallInst(CallInst &CI) {
   MachineInstr *TheCall;
   if (Function *F = CI.getCalledFunction()) {
     // Is it an intrinsic function call?
-    if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
+    if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
       visitIntrinsicCall(ID, CI);   // Special intrinsics are not handled here
       return;
     }
@@ -1066,29 +1068,29 @@ void ISel::visitCallInst(CallInst &CI) {
 }         
 
 
-void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
+void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
   unsigned TmpReg1, TmpReg2;
   switch (ID) {
-  case LLVMIntrinsic::va_start:
+  case Intrinsic::va_start:
     // Get the address of the first vararg value...
     TmpReg1 = getReg(CI);
     addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
     return;
 
-  case LLVMIntrinsic::va_copy:
+  case Intrinsic::va_copy:
     TmpReg1 = getReg(CI);
     TmpReg2 = getReg(CI.getOperand(1));
     BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
     return;
-  case LLVMIntrinsic::va_end: return;   // Noop on X86
+  case Intrinsic::va_end: return;   // Noop on X86
 
-  case LLVMIntrinsic::longjmp:
-  case LLVMIntrinsic::siglongjmp:
+  case Intrinsic::longjmp:
+  case Intrinsic::siglongjmp:
     BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true); 
     return;
 
-  case LLVMIntrinsic::setjmp:
-  case LLVMIntrinsic::sigsetjmp:
+  case Intrinsic::setjmp:
+  case Intrinsic::sigsetjmp:
     // Setjmp always returns zero...
     BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0);
     return;
@@ -1373,7 +1375,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
   switch (Class) {
   case cFP:              // Floating point divide
     if (isDiv) {
-      BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
+      BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
     } else {               // Floating point remainder...
       MachineInstr *TheCall =
         BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
@@ -1418,26 +1420,26 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
   unsigned ExtReg = ExtRegs[Class];
 
   // Put the first operand into one of the A registers...
-  BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
+  BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
 
   if (isSigned) {
     // Emit a sign extension instruction...
     unsigned ShiftResult = makeAnotherReg(Ty);
-    BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
-    BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
+    BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
+    BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
   } else {
     // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
-    BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
+    BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
   }
 
   // Emit the appropriate divide or remainder instruction...
-  BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
+  BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
 
   // Figure out which register we want to pick the result out of...
   unsigned DestReg = isDiv ? Reg : ExtReg;
   
   // Put the result into the destination register...
-  BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
+  BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
 }
 
 
@@ -2127,7 +2129,6 @@ void ISel::visitFreeInst(FreeInst &I) {
   doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
 }
    
-
 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
 /// into a machine code representation is a very simple peep-hole fashion.  The
 /// generated code sucks but the implementation is nice and simple.
@@ -2135,3 +2136,5 @@ void ISel::visitFreeInst(FreeInst &I) {
 FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) {
   return new ISel(TM);
 }
+
+} // End llvm namespace