- Added zero_reg def to stand for register 0.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 938e4cdc8fbf72092257d0921f195a0337bdad29..723954b2e07f694d848d2b0a368299d61e70f29a 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -109,6 +109,10 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // allocation used by the register allocator.
   //
   list<Register> MemberList = regList;
+  
+  // SubClassList - Specify which register classes correspond to subregisters
+  // of this class. The order should be by subregister set index.
+  list<RegisterClass> SubRegClassList = [];
 
   // MethodProtos/MethodBodies - These members can be used to insert arbitrary
   // code into a generated register class.   The normal usage of this is to 
@@ -183,10 +187,13 @@ class Instruction {
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit isReMaterializable = 0; // Is this instruction re-materializable?
+  bit isPredicable = 0;     // Is this instruction predicable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit noResults    = 0;     // Does this instruction produce no results?
+  bit clobbersPred = 0;     // Does it clobbers condition code / predicate?
+  bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
@@ -249,16 +256,33 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+/// zero_reg definition - Special node to stand for the zero register.
+///
+def zero_reg;
 
 /// PredicateOperand - This can be used to define a predicate operand for an
 /// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
 /// AlwaysVal specifies the value of this predicate when set to "always
-/// execute".
-class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
+/// execute". If isOutput is true, then this is output operand. If isImmutable
+/// is true, then the operand should not change after instruction selection.
+class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
+  : Operand<ty> {
   let MIOperandInfo = OpTypes;
+  bit isOutput = 0;
+  bit isImmutable = 0;
   dag ExecuteAlways = AlwaysVal;
 }
 
+class ImmutablePredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
+  : PredicateOperand<ty, OpTypes, AlwaysVal> {
+  let isImmutable = 1;
+}
+
+class PredicateDefOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
+  : PredicateOperand<ty, OpTypes, AlwaysVal> {
+  let isOutput = 1;
+}
+
 
 // InstrInfo - This class should only be instantiated once to provide parameters
 // which are global to the the target machine.
@@ -338,7 +362,8 @@ class Target {
 //===----------------------------------------------------------------------===//
 // SubtargetFeature - A characteristic of the chip set.
 //
-class SubtargetFeature<string n, string a,  string v, string d> {
+class SubtargetFeature<string n, string a,  string v, string d,
+                       list<SubtargetFeature> i = []> {
   // Name - Feature name.  Used by command line (-mattr=) to determine the
   // appropriate target chip.
   //
@@ -356,6 +381,11 @@ class SubtargetFeature<string n, string a,  string v, string d> {
   // information.
   //
   string Desc = d;
+
+  // Implies - Features that this feature implies are present. If one of those
+  // features isn't set, then this one shouldn't be set either.
+  //
+  list<SubtargetFeature> Implies = i;
 }
 
 //===----------------------------------------------------------------------===//