#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCRegisterInfo.h"
+#include "PPCSubtarget.h"
#include "llvm/Constants.h"
#include "llvm/Type.h"
#include "llvm/CodeGen/ValueTypes.h"
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// PPC::F14, return the number that it corresponds to (e.g. 14).
unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
+ using namespace PPC;
switch (RegEnum) {
- case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
- case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
- case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
- case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
- case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
- case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
- case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
- case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
- case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
- case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
- case PPC::R10: case PPC::F10: case PPC::V10: return 10;
- case PPC::R11: case PPC::F11: case PPC::V11: return 11;
- case PPC::R12: case PPC::F12: case PPC::V12: return 12;
- case PPC::R13: case PPC::F13: case PPC::V13: return 13;
- case PPC::R14: case PPC::F14: case PPC::V14: return 14;
- case PPC::R15: case PPC::F15: case PPC::V15: return 15;
- case PPC::R16: case PPC::F16: case PPC::V16: return 16;
- case PPC::R17: case PPC::F17: case PPC::V17: return 17;
- case PPC::R18: case PPC::F18: case PPC::V18: return 18;
- case PPC::R19: case PPC::F19: case PPC::V19: return 19;
- case PPC::R20: case PPC::F20: case PPC::V20: return 20;
- case PPC::R21: case PPC::F21: case PPC::V21: return 21;
- case PPC::R22: case PPC::F22: case PPC::V22: return 22;
- case PPC::R23: case PPC::F23: case PPC::V23: return 23;
- case PPC::R24: case PPC::F24: case PPC::V24: return 24;
- case PPC::R25: case PPC::F25: case PPC::V25: return 25;
- case PPC::R26: case PPC::F26: case PPC::V26: return 26;
- case PPC::R27: case PPC::F27: case PPC::V27: return 27;
- case PPC::R28: case PPC::F28: case PPC::V28: return 28;
- case PPC::R29: case PPC::F29: case PPC::V29: return 29;
- case PPC::R30: case PPC::F30: case PPC::V30: return 30;
- case PPC::R31: case PPC::F31: case PPC::V31: return 31;
- default:
- std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
- abort();
+ case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
+ case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
+ case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
+ case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
+ case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
+ case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
+ case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
+ case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
+ case R8 : case X8 : case F8 : case V8 : return 8;
+ case R9 : case X9 : case F9 : case V9 : return 9;
+ case R10: case X10: case F10: case V10: return 10;
+ case R11: case X11: case F11: case V11: return 11;
+ case R12: case X12: case F12: case V12: return 12;
+ case R13: case X13: case F13: case V13: return 13;
+ case R14: case X14: case F14: case V14: return 14;
+ case R15: case X15: case F15: case V15: return 15;
+ case R16: case X16: case F16: case V16: return 16;
+ case R17: case X17: case F17: case V17: return 17;
+ case R18: case X18: case F18: case V18: return 18;
+ case R19: case X19: case F19: case V19: return 19;
+ case R20: case X20: case F20: case V20: return 20;
+ case R21: case X21: case F21: case V21: return 21;
+ case R22: case X22: case F22: case V22: return 22;
+ case R23: case X23: case F23: case V23: return 23;
+ case R24: case X24: case F24: case V24: return 24;
+ case R25: case X25: case F25: case V25: return 25;
+ case R26: case X26: case F26: case V26: return 26;
+ case R27: case X27: case F27: case V27: return 27;
+ case R28: case X28: case F28: case V28: return 28;
+ case R29: case X29: case F29: case V29: return 29;
+ case R30: case X30: case F30: case V30: return 30;
+ case R31: case X31: case F31: case V31: return 31;
+ default:
+ std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
+ abort();
}
}
-PPCRegisterInfo::PPCRegisterInfo()
- : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
+PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
+ : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+ Subtarget(ST) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
+ // FIXME: We use R0 here, because it isn't available for RA.
// We need to store the CR in the low 4-bits of the saved value. First,
// issue a MFCR to save all of the CRBits.
- BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
+ BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
// If the saved register wasn't CR0, shift the bits left so that they are in
// CR0's slot.
if (SrcReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
- // rlwinm r11, r11, ShiftBits, 0, 31.
- BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
- .addReg(PPC::R11).addImm(ShiftBits).addImm(0).addImm(31);
+ // rlwinm r0, r0, ShiftBits, 0, 31.
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
}
- addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
- addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
+ // FIXME: We use R0 here, because it isn't available for RA.
+ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
// If the reloaded register isn't CR0, shift the bits right so that they are
// in the right CR's slot.
if (DestReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
- BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
- .addReg(PPC::R11).addImm(32-ShiftBits).addImm(0).addImm(31);
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
}
- BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
+ BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
if (RC == PPC::GPRCRegisterClass) {
- BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC::G8RCRegisterClass) {
BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC::F4RCRegisterClass) {
}
const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
- PPC::R1, PPC::R13,
- PPC::R14, PPC::R15,
- PPC::R16, PPC::R17,
- PPC::R18, PPC::R19,
- PPC::R20, PPC::R21,
- PPC::R22, PPC::R23,
- PPC::R24, PPC::R25,
- PPC::R26, PPC::R27,
- PPC::R28, PPC::R29,
- PPC::R30, PPC::R31,
- PPC::F14, PPC::F15,
- PPC::F16, PPC::F17,
- PPC::F18, PPC::F19,
- PPC::F20, PPC::F21,
- PPC::F22, PPC::F23,
- PPC::F24, PPC::F25,
- PPC::F26, PPC::F27,
- PPC::F28, PPC::F29,
+ // 32-bit Darwin calling convention.
+ static const unsigned Darwin32_CalleeSaveRegs[] = {
+ PPC::R1 , PPC::R13, PPC::R14, PPC::R15,
+ PPC::R16, PPC::R17, PPC::R18, PPC::R19,
+ PPC::R20, PPC::R21, PPC::R22, PPC::R23,
+ PPC::R24, PPC::R25, PPC::R26, PPC::R27,
+ PPC::R28, PPC::R29, PPC::R30, PPC::R31,
+
+ PPC::F14, PPC::F15, PPC::F16, PPC::F17,
+ PPC::F18, PPC::F19, PPC::F20, PPC::F21,
+ PPC::F22, PPC::F23, PPC::F24, PPC::F25,
+ PPC::F26, PPC::F27, PPC::F28, PPC::F29,
+ PPC::F30, PPC::F31,
+
+ PPC::CR2, PPC::CR3, PPC::CR4,
+ PPC::V20, PPC::V21, PPC::V22, PPC::V23,
+ PPC::V24, PPC::V25, PPC::V26, PPC::V27,
+ PPC::V28, PPC::V29, PPC::V30, PPC::V31,
+
+ PPC::LR, 0
+ };
+ // 64-bit Darwin calling convention.
+ static const unsigned Darwin64_CalleeSaveRegs[] = {
+ PPC::X1 , PPC::X13, PPC::X14, PPC::X15,
+ PPC::X16, PPC::X17, PPC::X18, PPC::X19,
+ PPC::X20, PPC::X21, PPC::X22, PPC::X23,
+ PPC::X24, PPC::X25, PPC::X26, PPC::X27,
+ PPC::X28, PPC::X29, PPC::X30, PPC::X31,
+
+ PPC::F14, PPC::F15, PPC::F16, PPC::F17,
+ PPC::F18, PPC::F19, PPC::F20, PPC::F21,
+ PPC::F22, PPC::F23, PPC::F24, PPC::F25,
+ PPC::F26, PPC::F27, PPC::F28, PPC::F29,
PPC::F30, PPC::F31,
- PPC::CR2, PPC::CR3,
- PPC::CR4, PPC::V20,
- PPC::V21, PPC::V22,
- PPC::V23, PPC::V24,
- PPC::V25, PPC::V26,
- PPC::V27, PPC::V28,
- PPC::V29, PPC::V30,
- PPC::V31, PPC::LR, 0
+
+ PPC::CR2, PPC::CR3, PPC::CR4,
+ PPC::V20, PPC::V21, PPC::V22, PPC::V23,
+ PPC::V24, PPC::V25, PPC::V26, PPC::V27,
+ PPC::V28, PPC::V29, PPC::V30, PPC::V31,
+
+ PPC::LR, 0
};
- return CalleeSaveRegs;
+
+ return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
+ Darwin32_CalleeSaveRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::GPRCRegClass, &PPC::GPRCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::F8RCRegClass, &PPC::F8RCRegClass,
- &PPC::CRRCRegClass, &PPC::CRRCRegClass,
- &PPC::CRRCRegClass, &PPC::VRRCRegClass,
- &PPC::VRRCRegClass, &PPC::VRRCRegClass,
- &PPC::VRRCRegClass, &PPC::VRRCRegClass,
- &PPC::VRRCRegClass, &PPC::VRRCRegClass,
- &PPC::VRRCRegClass, &PPC::VRRCRegClass,
- &PPC::VRRCRegClass, &PPC::VRRCRegClass,
- &PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
+ // 32-bit Darwin calling convention.
+ static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
+ &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
+ &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
+ &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
+ &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
+ &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
+
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,
+
+ &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
+
+ &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
+ &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
+ &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
+
+ &PPC::GPRCRegClass, 0
};
- return CalleeSaveRegClasses;
+
+ // 64-bit Darwin calling convention.
+ static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
+ &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
+ &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
+ &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
+ &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
+ &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
+
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
+ &PPC::F8RCRegClass,&PPC::F8RCRegClass,
+
+ &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
+
+ &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
+ &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
+ &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
+
+ &PPC::GPRCRegClass, 0
+ };
+
+ return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
+ Darwin32_CalleeSaveRegClasses;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
- if ((Opc == PPC::OR4 &&
+ if ((Opc == PPC::OR &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
//
static bool hasFP(const MachineFunction &MF) {
const MachineFrameInfo *MFI = MF.getFrameInfo();
- unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
// If frame pointers are forced, or if there are variable sized stack objects,
// use a frame pointer.
MachineBasicBlock::iterator I) const {
if (hasFP(MF)) {
// If we have a frame pointer, convert as follows:
- // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
+ // ADJCALLSTACKDOWN -> lwz r0, 0(r31)
+ // stwu, r0, -amount(r1)
// ADJCALLSTACKUP -> addi, r1, r1, amount
MachineInstr *Old = I;
unsigned Amount = Old->getOperand(0).getImmedValue();
// Replace the pseudo instruction with a new instruction...
if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
- BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
+ BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31);
+ BuildMI(MBB, I, PPC::STWU, 3)
+ .addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1);
} else {
assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
int FrameIndex = MI.getOperand(i).getFrameIndex();
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
- MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
+ MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
// Take into account whether it's an add or mem instruction
unsigned OffIdx = (i == 2) ? 1 : 2;
+ // Figure out if the offset in the instruction is shifted right two bits. This
+ // is true for instructions like "STD", which the machine implicitly adds two
+ // low zeros to.
+ bool isIXAddr = false;
+ switch (MI.getOpcode()) {
+ case PPC::LWA:
+ case PPC::LD:
+ case PPC::STD:
+ case PPC::STD_32:
+ isIXAddr = true;
+ break;
+ }
+
+
// Now add the frame object offset to the offset from r1.
- int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
- MI.getOperand(OffIdx).getImmedValue();
+ int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
+
+ if (!isIXAddr)
+ Offset += MI.getOperand(OffIdx).getImmedValue();
+ else
+ Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
// If we're not using a Frame Pointer that has been set to the value of the
// SP before having the stack size subtracted from it, then add the stack size
"No indexed form of load or store available!");
unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
MI.setOpcode(NewOpcode);
- MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
- MI.getOperand(2).ChangeToRegister(PPC::R0);
+ MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
+ MI.getOperand(2).ChangeToRegister(PPC::R0, false);
} else {
- switch (MI.getOpcode()) {
- case PPC::LWA:
- case PPC::LD:
- case PPC::STD:
- case PPC::STD_32:
+ if (isIXAddr) {
assert((Offset & 3) == 0 && "Invalid frame offset!");
Offset >>= 2; // The actual encoded value has the low two bits zero.
- break;
}
MI.getOperand(OffIdx).ChangeToImmediate(Offset);
}
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
// of the stack and round the size to a multiple of the alignment.
unsigned Align = std::max(TargetAlign, MaxAlign);
- unsigned GPRSize = 4;
+ unsigned GPRSize = Subtarget.isPPC64() ? 8 : 4;
unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
// Adjust stack pointer: r1 -= numbytes.
// If there is a preferred stack alignment, align R1 now
- if (MaxAlign > TargetAlign) {
- assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
- assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
- BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
- .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
- BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
- .addImm(0-NumBytes);
- BuildMI(MBB, MBBI, PPC::STWUX, 3)
- .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
- } else if (NumBytes <= 32768) {
- BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
- .addReg(PPC::R1);
- } else {
- BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
- BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
- .addImm(NegNumbytes & 0xFFFF);
- BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
- .addReg(PPC::R0);
+ if (!Subtarget.isPPC64()) {
+ // PPC32.
+ if (MaxAlign > TargetAlign) {
+ assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767&&"Invalid alignment!");
+ assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
+ BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
+ BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
+ .addImm(0-NumBytes);
+ BuildMI(MBB, MBBI, PPC::STWUX, 3)
+ .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+ } else if (NumBytes <= 32768) {
+ BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
+ .addReg(PPC::R1);
+ } else {
+ BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
+ BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(NegNumbytes & 0xFFFF);
+ BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
+ .addReg(PPC::R0);
+ }
+ } else { // PPC64.
+ if (MaxAlign > TargetAlign) {
+ assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767&&"Invalid alignment!");
+ assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
+ BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0)
+ .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
+ BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0)
+ .addImm(0-NumBytes);
+ BuildMI(MBB, MBBI, PPC::STDUX, 3)
+ .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
+ } else if (NumBytes <= 32768*4) {
+ BuildMI(MBB, MBBI, PPC::STDU, 3).addReg(PPC::X1).addImm(NegNumbytes/4)
+ .addReg(PPC::X1);
+ } else {
+ BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegNumbytes >> 16);
+ BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
+ .addImm(NegNumbytes & 0xFFFF);
+ BuildMI(MBB, MBBI, PPC::STDUX, 3).addReg(PPC::X1).addReg(PPC::X1)
+ .addReg(PPC::X0);
+ }
}
if (DebugInfo && DebugInfo->hasInfo()) {
std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
unsigned LabelID = DebugInfo->NextLabelID();
- // Show update of SP.
- MachineLocation Dst(MachineLocation::VirtualFP);
- MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
- Moves.push_back(new MachineMove(LabelID, Dst, Src));
-
+ // Mark effective beginning of when frame pointer becomes valid.
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
+
+ // Show update of SP.
+ MachineLocation SPDst(MachineLocation::VirtualFP);
+ MachineLocation SPSrc(MachineLocation::VirtualFP, NegNumbytes);
+ Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc));
+
+ // Add callee saved registers to move list.
+ const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
+ for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
+ MachineLocation CSDst(MachineLocation::VirtualFP,
+ MFI->getObjectOffset(CSI[I].getFrameIdx()));
+ MachineLocation CSSrc(CSI[I].getReg());
+ Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc));
+ }
}
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
if (HasFP) {
- BuildMI(MBB, MBBI, PPC::STW, 3)
- .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
- BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
+ if (!Subtarget.isPPC64()) {
+ BuildMI(MBB, MBBI, PPC::STW, 3)
+ .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
+ BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
+ } else {
+ BuildMI(MBB, MBBI, PPC::STD, 3)
+ .addReg(PPC::X31).addImm(GPRSize/4).addReg(PPC::X1);
+ BuildMI(MBB, MBBI, PPC::OR8, 2, PPC::X31).addReg(PPC::X1).addReg(PPC::X1);
+ }
}
}
// If this function has a frame pointer, load the saved stack pointer from
// its stack slot.
if (hasFP(MF)) {
- BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
- .addImm(GPRSize).addReg(PPC::R31);
+ if (!Subtarget.isPPC64()) {
+ BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
+ .addImm(GPRSize).addReg(PPC::R31);
+ } else {
+ BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X31)
+ .addImm(GPRSize/4).addReg(PPC::X31);
+ }
}
- // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
+ // The loaded (or persistent) stack pointer value is offset by the 'stwu'
// on entry to the function. Add this offset back now.
- if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
- BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
- .addReg(PPC::R1).addImm(NumBytes);
+ if (!Subtarget.isPPC64()) {
+ if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
+ BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
+ .addReg(PPC::R1).addImm(NumBytes);
+ } else {
+ BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
+ }
} else {
- BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
+ if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
+ BuildMI(MBB, MBBI, PPC::ADDI8, 2, PPC::X1)
+ .addReg(PPC::X1).addImm(NumBytes);
+ } else {
+ BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X1).addImm(0).addReg(PPC::X1);
+ }
}
}
}
}
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
- return hasFP(MF) ? PPC::R31 : PPC::R1;
+ if (!Subtarget.isPPC64())
+ return hasFP(MF) ? PPC::R31 : PPC::R1;
+ else
+ return hasFP(MF) ? PPC::X31 : PPC::X1;
}
void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
const {
- // Initial state is the frame pointer is R1.
+ // Initial state of the frame pointer is R1.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(PPC::R1, 0);
Moves.push_back(new MachineMove(0, Dst, Src));
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