//===----------------------------------------------------------------------===//
#include "ARM.h"
+#include "ARMAddressingModes.h"
#include "ARMSubtarget.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
- ARMOperand *MaybeParseRegister(bool ParseWriteBack);
+ int TryParseRegister();
+ ARMOperand *TryParseRegisterWithWriteBack();
ARMOperand *ParseRegisterList();
ARMOperand *ParseMemory();
public:
ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
- : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
+ : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
+ // Initialize the set of available features.
+ setAvailableFeatures(ComputeAvailableFeatures(
+ &TM.getSubtarget<ARMSubtarget>()));
+ }
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
bool isMemMode5() const {
- // FIXME: Is this right? What about postindexed and Writeback?
if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
- Mem.Preindexed || Mem.Negative)
+ Mem.Writeback || Mem.Negative)
return false;
-
- return true;
+ // If there is an offset expression, make sure it's valid.
+ if (!Mem.Offset)
+ return true;
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
+ if (!CE)
+ return false;
+ // The offset must be a multiple of 4 in the range 0-1020.
+ int64_t Value = CE->getValue();
+ return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
}
void addMemMode5Operands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
- addExpr(Inst, Mem.Offset);
+
+ // FIXME: #-0 is encoded differently than #0. Does the parser preserve
+ // the difference?
+ if (Mem.Offset) {
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
+ assert(CE && "Non-constant mode 5 offset operand!");
+
+ // The MCInst offset operand doesn't include the low two bits (like
+ // the instruction encoding).
+ int64_t Offset = CE->getValue() / 4;
+ if (Offset >= 0)
+ Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
+ Offset)));
+ else
+ Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
+ -Offset)));
+ } else {
+ Inst.addOperand(MCOperand::CreateImm(0));
+ }
}
virtual void dump(raw_ostream &OS) const;
/// }
/// Try to parse a register name. The token must be an Identifier when called,
-/// and if it is a register name the token is eaten and a Reg operand is created
-/// and returned. Otherwise return null.
+/// and if it is a register name the token is eaten and the register number is
+/// returned. Otherwise return -1.
///
-/// TODO this is likely to change to allow different register types and or to
-/// parse for a specific register type.
-ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
- SMLoc S, E;
+int ARMAsmParser::TryParseRegister() {
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
// FIXME: Validate register for the current architecture; we have to do
// validation later, so maybe there is no need for this here.
- int RegNum;
-
- RegNum = MatchRegisterName(Tok.getString());
+ int RegNum = MatchRegisterName(Tok.getString());
if (RegNum == -1)
- return 0;
+ return -1;
+ Parser.Lex(); // Eat identifier token.
+ return RegNum;
+}
- S = Tok.getLoc();
- Parser.Lex(); // Eat identifier token.
+/// Try to parse a register name. The token must be an Identifier when called,
+/// and if it is a register name the token is eaten and the register number is
+/// returned. Otherwise return -1.
+///
+/// TODO this is likely to change to allow different register types and or to
+/// parse for a specific register type.
+ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
+ SMLoc S = Parser.getTok().getLoc();
+ int RegNo = TryParseRegister();
+ if (RegNo == -1) return 0;
- E = Parser.getTok().getLoc();
+ SMLoc E = Parser.getTok().getLoc();
bool Writeback = false;
- if (ParseWriteBack) {
- const AsmToken &ExclaimTok = Parser.getTok();
- if (ExclaimTok.is(AsmToken::Exclaim)) {
- E = ExclaimTok.getLoc();
- Writeback = true;
- Parser.Lex(); // Eat exclaim token
- }
+ const AsmToken &ExclaimTok = Parser.getTok();
+ if (ExclaimTok.is(AsmToken::Exclaim)) {
+ E = ExclaimTok.getLoc();
+ Writeback = true;
+ Parser.Lex(); // Eat exclaim token
}
- return ARMOperand::CreateReg(RegNum, Writeback, S, E);
+ return ARMOperand::CreateReg(RegNo, Writeback, S, E);
}
/// Parse a register list, return it if successful else return null. The first
Error(BaseRegTok.getLoc(), "register expected");
return 0;
}
- int BaseRegNum = 0;
- if (ARMOperand *Op = MaybeParseRegister(false)) {
- BaseRegNum = Op->getReg();
- delete Op;
- } else {
+ int BaseRegNum = TryParseRegister();
+ if (BaseRegNum == -1) {
Error(BaseRegTok.getLoc(), "register expected");
return 0;
}
}
// The "[Rn" we have so far was not followed by a comma.
else if (Tok.is(AsmToken::RBrac)) {
- // This is a post indexing addressing forms, that is a ']' follows after
- // the "[Rn".
- Postindexed = true;
- Writeback = true;
+ // If there's anything other than the right brace, this is a post indexing
+ // addressing form.
E = Tok.getLoc();
Parser.Lex(); // Eat right bracket token.
const AsmToken &NextTok = Parser.getTok();
if (NextTok.isNot(AsmToken::EndOfStatement)) {
+ Postindexed = true;
+ Writeback = true;
if (NextTok.isNot(AsmToken::Comma)) {
Error(NextTok.getLoc(), "',' expected");
return 0;
// See if there is a register following the "[Rn," or "[Rn]," we have so far.
const AsmToken &OffsetRegTok = Parser.getTok();
if (OffsetRegTok.is(AsmToken::Identifier)) {
- if (ARMOperand *Op = MaybeParseRegister(false)) {
+ SMLoc CurLoc = OffsetRegTok.getLoc();
+ OffsetRegNum = TryParseRegister();
+ if (OffsetRegNum != -1) {
OffsetIsReg = true;
- E = Op->getEndLoc();
- OffsetRegNum = Op->getReg();
- delete Op;
+ E = CurLoc;
}
}
+
// If we parsed a register as the offset then their can be a shift after that
if (OffsetRegNum != -1) {
// Look for a comma then a shift
switch (getLexer().getKind()) {
case AsmToken::Identifier:
- if (ARMOperand *Op = MaybeParseRegister(true))
+ if (ARMOperand *Op = TryParseRegisterWithWriteBack())
return Op;
// This was not a register so parse other operands that start with an
// FIXME: We need a way to check whether a prefix supports predication,
// otherwise we will end up with an ambiguity for instructions that happen to
// end with a predicate name.
+ // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
+ // indicates to update the condition codes. Those instructions have an
+ // additional immediate operand which encodes the prefix as reg0 or CPSR.
+ // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
+ // the SMMLS instruction.
unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
.Case("al", ARMCC::AL)
.Default(~0U);
- if (CC != ~0U)
- Head = Head.slice(0, Head.size() - 2);
- else
+ if (CC == ~0U ||
+ (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
CC = ARMCC::AL;
+ } else {
+ Head = Head.slice(0, Head.size() - 2);
+ }
Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
+ // FIXME: Should only add this operand for predicated instructions
Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
// Add the remaining tokens in the mnemonic.
projects / oota-llvm.git / blobdiff