#include "llvm/Target/TargetInstrInfo.h"
#include "ARMRegisterInfo.h"
+#include "ARM.h"
namespace llvm {
class ARMSubtarget;
// Instruction Flags.
//===------------------------------------------------------------------===//
- // This three-bit field describes the addressing mode used. Zero is unused
- // so that we can tell if we forgot to set a value.
+ // This four-bit field describes the addressing mode used.
AddrModeMask = 0xf,
AddrModeNone = 0,
AddrModeT1 = 6,
AddrModeT2 = 7,
AddrModeT4 = 8,
- AddrModeTs = 9, // i8 * 4 for pc and sp relative data
+ AddrModeTs = 9, // i8 * 4 for pc and sp relative data
// Size* - Flags to keep track of the size of an instruction.
SizeShift = 4,
IndexModePre = 1,
IndexModePost = 2,
- // Opcode
- OpcodeShift = 9,
- OpcodeMask = 0xf << OpcodeShift,
-
- // Format
- FormShift = 13,
- FormMask = 31 << FormShift,
+ //===------------------------------------------------------------------===//
+ // Misc flags.
+
+ // UnaryDP - Indicates this is a unary data processing instruction, i.e.
+ // it doesn't have a Rn operand.
+ UnaryDP = 1 << 9,
+
+ //===------------------------------------------------------------------===//
+ // Instruction encoding formats.
+ //
+ FormShift = 10,
+ FormMask = 0x1f << FormShift,
// Pseudo instructions
- Pseudo = 1 << FormShift,
+ Pseudo = 0 << FormShift,
// Multiply instructions
- MulFrm = 2 << FormShift,
- MulSMLAW = 3 << FormShift,
- MulSMULW = 4 << FormShift,
- MulSMLA = 5 << FormShift,
- MulSMUL = 6 << FormShift,
+ MulFrm = 1 << FormShift,
// Branch instructions
- Branch = 7 << FormShift,
- BranchMisc = 8 << FormShift,
+ BrFrm = 2 << FormShift,
+ BrMiscFrm = 3 << FormShift,
// Data Processing instructions
- DPRdIm = 9 << FormShift,
- DPRdReg = 10 << FormShift,
- DPRdSoReg = 11 << FormShift,
- DPRdMisc = 12 << FormShift,
-
- DPRnIm = 13 << FormShift,
- DPRnReg = 14 << FormShift,
- DPRnSoReg = 15 << FormShift,
-
- DPRIm = 16 << FormShift,
- DPRReg = 17 << FormShift,
- DPRSoReg = 18 << FormShift,
-
- DPRImS = 19 << FormShift,
- DPRRegS = 20 << FormShift,
- DPRSoRegS = 21 << FormShift,
+ DPFrm = 4 << FormShift,
+ DPSoRegFrm = 5 << FormShift,
// Load and Store
- LdFrm = 22 << FormShift,
- StFrm = 23 << FormShift,
+ LdFrm = 6 << FormShift,
+ StFrm = 7 << FormShift,
+ LdMiscFrm = 8 << FormShift,
+ StMiscFrm = 9 << FormShift,
+ LdStMulFrm = 10 << FormShift,
// Miscellaneous arithmetic instructions
- ArithMisc = 24 << FormShift,
+ ArithMiscFrm = 11 << FormShift,
+
+ // Extend instructions
+ ExtFrm = 12 << FormShift,
+
+ // VFP formats
+ VFPUnaryFrm = 13 << FormShift,
+ VFPBinaryFrm = 14 << FormShift,
+ VFPConv1Frm = 15 << FormShift,
+ VFPConv2Frm = 16 << FormShift,
+ VFPConv3Frm = 17 << FormShift,
+ VFPConv4Frm = 18 << FormShift,
+ VFPConv5Frm = 19 << FormShift,
+ VFPLdStFrm = 20 << FormShift,
+ VFPLdStMulFrm = 21 << FormShift,
+ VFPMiscFrm = 22 << FormShift,
// Thumb format
- ThumbFrm = 25 << FormShift,
-
- // VFP format
- VPFFrm = 26 << FormShift,
+ ThumbFrm = 23 << FormShift,
+ //===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
// machine instructions.
- RegRsShift = 8,
- RegRdShift = 12,
- RegRnShift = 16,
- L_BitShift = 20,
- S_BitShift = 20,
- U_BitShift = 23,
- IndexShift = 24,
- I_BitShift = 25
+ M_BitShift = 5,
+ ShiftImmShift = 5,
+ ShiftShift = 7,
+ N_BitShift = 7,
+ ImmHiShift = 8,
+ SoRotImmShift = 8,
+ RegRsShift = 8,
+ ExtRotImmShift = 10,
+ RegRdLoShift = 12,
+ RegRdShift = 12,
+ RegRdHiShift = 16,
+ RegRnShift = 16,
+ S_BitShift = 20,
+ W_BitShift = 21,
+ AM3_I_BitShift = 22,
+ D_BitShift = 22,
+ U_BitShift = 23,
+ P_BitShift = 24,
+ I_BitShift = 25,
+ CondShift = 28
};
}
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
///
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const;
- virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
- virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+ virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
+ int &FrameIndex) const;
+ virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
+ int &FrameIndex) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
- LiveVariables &LV) const;
+ LiveVariables *LV) const;
// Branch analysis.
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
- std::vector<MachineOperand> &Cond) const;
+ SmallVectorImpl<MachineOperand> &Cond) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
- const std::vector<MachineOperand> &Cond) const;
- virtual void copyRegToReg(MachineBasicBlock &MBB,
+ const SmallVectorImpl<MachineOperand> &Cond) const;
+ virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const;
- virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
- MachineInstr* MI,
- SmallVectorImpl<unsigned> &Ops,
- int FrameIndex) const;
-
- virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
- MachineInstr* MI,
- SmallVectorImpl<unsigned> &Ops,
- MachineInstr* LoadMI) const {
+ virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
+ MachineInstr* MI,
+ const SmallVectorImpl<unsigned> &Ops,
+ int FrameIndex) const;
+
+ virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
+ MachineInstr* MI,
+ const SmallVectorImpl<unsigned> &Ops,
+ MachineInstr* LoadMI) const {
return 0;
}
- virtual bool canFoldMemoryOperand(MachineInstr *MI,
- SmallVectorImpl<unsigned> &Ops) const;
+ virtual bool canFoldMemoryOperand(const MachineInstr *MI,
+ const SmallVectorImpl<unsigned> &Ops) const;
- virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
- virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
+ virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
+ virtual
+ bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
// Predication support.
virtual bool isPredicated(const MachineInstr *MI) const;
+ ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
+ int PIdx = MI->findFirstPredOperandIdx();
+ return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
+ : ARMCC::AL;
+ }
+
virtual
bool PredicateInstruction(MachineInstr *MI,
- const std::vector<MachineOperand> &Pred) const;
+ const SmallVectorImpl<MachineOperand> &Pred) const;
virtual
- bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
- const std::vector<MachineOperand> &Pred2) const;
+ bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
+ const SmallVectorImpl<MachineOperand> &Pred2) const;
virtual bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const;
+
+ /// GetInstSize - Returns the size of the specified MachineInstr.
+ ///
+ virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
};
- // Utility routines
- namespace ARM {
- /// GetInstSize - Returns the size of the specified MachineInstr.
- ///
- unsigned GetInstSize(MachineInstr *MI);
-
- /// GetFunctionSize - Returns the size of the specified MachineFunction.
- ///
- unsigned GetFunctionSize(MachineFunction &MF);
- }
}
#endif
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