#define DEBUG_TYPE "reg-scavenging"
/// setUsed - Set the register units of this register as used.
-void RegScavenger::setRegUsed(unsigned Reg) {
- for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
- RegUnitsAvailable.reset(*RUI);
+void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
+ for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
+ LaneBitmask UnitMask = (*RUI).second;
+ if (UnitMask == 0 || (LaneMask & UnitMask) != 0)
+ RegUnitsAvailable.reset((*RUI).first);
+ }
}
void RegScavenger::initRegState() {
return;
// Live-in registers are in use.
- for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
- E = MBB->livein_end(); I != E; ++I)
- setRegUsed(*I);
+ for (const auto &LI : MBB->liveins())
+ setRegUsed(LI.PhysReg, LI.LaneMask);
// Pristine CSRs are also unavailable.
const MachineFunction &MF = *MBB->getParent();
// Find out which registers are early clobbered, killed, defined, and marked
// def-dead in this instruction.
- // FIXME: The scavenger is not predication aware. If the instruction is
- // predicated, conservatively assume "kill" markers do not actually kill the
- // register. Similarly ignores "dead" markers.
- bool isPred = TII->isPredicated(MI);
KillRegUnits.reset();
DefRegUnits.reset();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
}
// Apply the mask.
- (isPred ? DefRegUnits : KillRegUnits) |= TmpRegUnits;
+ KillRegUnits |= TmpRegUnits;
}
if (!MO.isReg())
continue;
// Ignore undef uses.
if (MO.isUndef())
continue;
- if (!isPred && MO.isKill())
+ if (MO.isKill())
addRegUnits(KillRegUnits, Reg);
} else {
assert(MO.isDef());
- if (!isPred && MO.isDead())
+ if (MO.isDead())
addRegUnits(KillRegUnits, Reg);
else
addRegUnits(DefRegUnits, Reg);