*v0.0.4:
* 1) add clock information in struct camsys_devio_name_s;
*v0.0.5:
- 1) add pwren control
+* 1) add pwren control
+*v0.6.0:
+* 1) add support mipi phy configuration;
+* 2) add support io domain and mclk driver strength configuration;
+*v0.7.0:
+ 1) add flash_trigger_out control
+*v0.8.0:
+ 1) support isp iommu
+*v0.9.0:
+ 1) add dev_name in struct camsys_devio_name_s;
+*v0.a.0:
+ 1) support external flash IC
+*v0.b.0:
+ 1) add CamSys_SensorBit0_CifBit4 in enum camsys_cifio_e.
*/
-#define CAMSYS_HEAD_VERSION KERNEL_VERSION(0,0,5)
+#define CAMSYS_HEAD_VERSION KERNEL_VERSION(0,0xb,0)
#define CAMSYS_MARVIN_DEVNAME "camsys_marvin"
#define CAMSYS_CIF0_DEVNAME "camsys_cif0"
} camsys_reginfo_t;
typedef enum camsys_sysctrl_ops_e {
- CamSys_Avdd =0,
+
+ CamSys_Vdd_Start_Tag,
+ CamSys_Avdd,
CamSys_Dovdd,
CamSys_Dvdd,
CamSys_Afvdd,
+ CamSys_Vdd_End_Tag,
- CamSys_Vdd_Tag = 10,
-
+ CamSys_Gpio_Start_Tag,
CamSys_PwrDn,
CamSys_Rst,
CamSys_AfPwr,
CamSys_AfPwrDn,
- CamSys_PwrEn,
+ CamSys_PwrEn,
+ CamSys_Gpio_End_Tag,
+
+ CamSys_Clk_Start_Tag,
+ CamSys_ClkIn,
+ CamSys_Clk_End_Tag,
+
+ CamSys_Phy_Start_Tag,
+ CamSys_Phy,
+ CamSys_Phy_End_Tag,
+ CamSys_Flash_Trigger_Start_Tag,
+ CamSys_Flash_Trigger,
+ CamSys_Flash_Trigger_End_Tag,
+ CamSys_IOMMU
- CamSys_Gpio_Tag = 50,
-
- CamSys_ClkIn
} camsys_sysctrl_ops_t;
typedef struct camsys_regulator_info_s {
unsigned int active;
} camsys_gpio_info_t;
+typedef struct camsys_iommu_s{
+ int client_fd;
+ int map_fd;
+ unsigned long linear_addr;
+ unsigned long len;
+}camsys_iommu_t;
+
typedef struct camsys_sysctrl_s {
unsigned int dev_mask;
camsys_sysctrl_ops_t ops;
unsigned int on;
+
+ unsigned int rev[20];
} camsys_sysctrl_t;
typedef struct camsys_flash_info_s {
- camsys_gpio_info_t fl;
+ unsigned char fl_drv_name[CAMSYS_NAME_LEN];
+ camsys_gpio_info_t fl; //fl_trig
+ camsys_gpio_info_t fl_en;
} camsys_flash_info_t;
typedef struct camsys_mipiphy_s {
- unsigned int data_en_bit; //data lane enable bit;
- #if 0
- unsigned int freq;
- unsigned int phy_index; //phy0,phy1
- #endif
+ unsigned int data_en_bit; // data lane enable bit;
+ unsigned int bit_rate; // Mbps/lane
+ unsigned int phy_index; // phy0,phy1
} camsys_mipiphy_t;
typedef enum camsys_fmt_e {
CamSys_Fmt_Raw_14b = 0x2d,
} camsys_fmt_t;
+typedef enum camsys_cifio_e {
+ CamSys_SensorBit0_CifBit0 = 0x00,
+ CamSys_SensorBit0_CifBit2 = 0x01,
+ CamSys_SensorBit0_CifBit4 = 0x02,
+} camsys_cifio_t;
+
typedef struct camsys_cifphy_s {
unsigned int cif_num;
camsys_fmt_t fmt;
+ camsys_cifio_t cifio;
+
} camsys_cifphy_t;
typedef enum camsys_phy_type_e {
typedef struct camsys_extdev_clk_s {
unsigned int in_rate;
+ unsigned int driver_strength; //0 - 3
} camsys_extdev_clk_t;
typedef struct camsys_devio_name_s {
+ unsigned char dev_name[CAMSYS_NAME_LEN];
unsigned int dev_id;
camsys_regulator_info_t avdd; // sensor avdd power regulator name
camsys_gpio_info_t rst; // hard reset gpio name
camsys_gpio_info_t afpwr; // auto focus vcm driver ic power gpio name
camsys_gpio_info_t afpwrdn; // auto focus vcm driver ic standby gpio
- camsys_gpio_info_t pwren; // power enable gpio name
+ camsys_gpio_info_t pwren; // power enable gpio name
camsys_flash_info_t fl;
*
*/
#define CAMSYS_IOC_MAGIC 'M'
-#define CAMSYS_IOC_MAXNR 12
+#define CAMSYS_IOC_MAXNR 14
#define CAMSYS_VERCHK _IOR(CAMSYS_IOC_MAGIC, 0, camsys_version_t)
#define CAMSYS_IRQDISCONNECT _IOW(CAMSYS_IOC_MAGIC, 10, camsys_irqcnnt_t)
#define CAMSYS_QUREYMEM _IOR(CAMSYS_IOC_MAGIC, 11, camsys_querymem_t)
+#define CAMSYS_QUREYIOMMU _IOW(CAMSYS_IOC_MAGIC, 12, int)
#endif