MC: Allow modifiers in MCSymbolRefExpr, and eliminate X86MCTargetExpr.

[oota-llvm.git] / include / llvm / MC / MCInst.h

diff --git a/include/llvm/MC/MCInst.h b/include/llvm/MC/MCInst.h
index 4f7e6cf0b493f95b28e7d6e30e558a797a640407..29b38dd15d119b224e957c30c7511aca7ea9ad5d 100644 (file)
--- a/include/llvm/MC/MCInst.h
+++ b/include/llvm/MC/MCInst.h
@@ -13,15 +13,16 @@
 //
 //===----------------------------------------------------------------------===//
 
-
 #ifndef LLVM_MC_MCINST_H
 #define LLVM_MC_MCINST_H
 
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/DataTypes.h"
-#include "llvm/Support/DebugLoc.h"
+#include "llvm/System/DataTypes.h"
 
 namespace llvm {
+class raw_ostream;
+class MCAsmInfo;
+class MCExpr;
 
 /// MCOperand - Instances of this class represent operands of the MCInst class.
 /// This is a simple discriminated union.
@@ -29,21 +30,24 @@ class MCOperand {
   enum MachineOperandType {
     kInvalid,                 ///< Uninitialized.
     kRegister,                ///< Register operand.
-    kImmediate                ///< Immediate operand.
+    kImmediate,               ///< Immediate operand.
+    kExpr                     ///< Relocatable immediate operand.
   };
   unsigned char Kind;
   
   union {
     unsigned RegVal;
-    uint64_t ImmVal;
+    int64_t ImmVal;
+    const MCExpr *ExprVal;
   };
 public:
   
   MCOperand() : Kind(kInvalid) {}
-  MCOperand(const MCOperand &RHS) { *this = RHS; }
 
+  bool isValid() const { return Kind != kInvalid; }
   bool isReg() const { return Kind == kRegister; }
   bool isImm() const { return Kind == kImmediate; }
+  bool isExpr() const { return Kind == kExpr; }
   
   /// getReg - Returns the register number.
   unsigned getReg() const {
@@ -57,23 +61,45 @@ public:
     RegVal = Reg;
   }
   
-  uint64_t getImm() const {
+  int64_t getImm() const {
     assert(isImm() && "This is not an immediate");
     return ImmVal;
   }
-  void setImm(uint64_t Val) {
+  void setImm(int64_t Val) {
     assert(isImm() && "This is not an immediate");
     ImmVal = Val;
   }
   
-  void MakeReg(unsigned Reg) {
-    Kind = kRegister;
-    RegVal = Reg;
+  const MCExpr *getExpr() const {
+    assert(isExpr() && "This is not an expression");
+    return ExprVal;
   }
-  void MakeImm(uint64_t Val) {
-    Kind = kImmediate;
-    ImmVal = Val;
+  void setExpr(const MCExpr *Val) {
+    assert(isExpr() && "This is not an expression");
+    ExprVal = Val;
+  }
+  
+  static MCOperand CreateReg(unsigned Reg) {
+    MCOperand Op;
+    Op.Kind = kRegister;
+    Op.RegVal = Reg;
+    return Op;
+  }
+  static MCOperand CreateImm(int64_t Val) {
+    MCOperand Op;
+    Op.Kind = kImmediate;
+    Op.ImmVal = Val;
+    return Op;
+  }
+  static MCOperand CreateExpr(const MCExpr *Val) {
+    MCOperand Op;
+    Op.Kind = kExpr;
+    Op.ExprVal = Val;
+    return Op;
   }
+
+  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
+  void dump() const;
 };
 
   
@@ -83,13 +109,22 @@ class MCInst {
   unsigned Opcode;
   SmallVector<MCOperand, 8> Operands;
 public:
-  MCInst() : Opcode(~0U) {}
+  MCInst() : Opcode(0) {}
   
-  unsigned getOpcode() const { return Opcode; }
-  DebugLoc getDebugLoc() const { return DebugLoc(); }
+  void setOpcode(unsigned Op) { Opcode = Op; }
   
+  unsigned getOpcode() const { return Opcode; }
+
   const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
+  MCOperand &getOperand(unsigned i) { return Operands[i]; }
+  unsigned getNumOperands() const { return Operands.size(); }
   
+  void addOperand(const MCOperand &Op) {
+    Operands.push_back(Op);
+  }
+
+  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
+  void dump() const;
 };