-//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
+//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the MachineInstr class, which is the
// basic representation for all target dependent machine instructions used by
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H
-#include "llvm/Target/MRegisterInfo.h"
#include "Support/Annotation.h"
#include "Support/iterator"
-#include <set>
+#include <vector>
+
+namespace llvm {
class Value;
class Function;
private:
// Bit fields of the flags variable used for different operand properties
enum {
- DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
- DEFUSEFLAG = 0x02, // this is both a def and a use
+ DEFFLAG = 0x01, // this is a def of the operand
+ USEFLAG = 0x02, // this is a use of the operand
HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
-
- USEDEFMASK = 0x03,
};
private:
opType(OpTy),
regNum(Reg) {
switch (UseTy) {
- case MOTy::Use: flags = 0; break;
- case MOTy::Def: flags = DEFONLYFLAG; break;
- case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ case MOTy::Use: flags = USEFLAG; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
default: assert(0 && "Invalid value for UseTy!");
}
}
bool isPCRelative = false)
: value(V), opType(OpTy), regNum(-1) {
switch (UseTy) {
- case MOTy::Use: flags = 0; break;
- case MOTy::Def: flags = DEFONLYFLAG; break;
- case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ case MOTy::Use: flags = USEFLAG; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
default: assert(0 && "Invalid value for UseTy!");
}
if (isPCRelative) flags |= PCRELATIVE;
bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
- // This is to finally stop caring whether we have a virtual or machine
- // register -- an easier interface is to simply call both virtual and machine
- // registers essentially the same, yet be able to distinguish when
- // necessary. Thus the instruction selector can just add registers without
- // abandon, and the register allocator won't be confused.
- bool isVirtualRegister() const {
- return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
- && regNum >= MRegisterInfo::FirstVirtualRegister;
- }
- bool isPhysicalRegister() const {
- return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
- && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
- }
- bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
- bool isMachineRegister() const { return !isVirtualRegister(); }
+ /// isRegister - Return true if this operand is a register operand.
+ ///
+ /// Note: In the sparc backend, this only returns true for "machine
+ /// registers", not for "virtual registers".
+ ///
+ bool isRegister() const { return opType == MO_MachineRegister; }
+
bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
bool isImmediate() const {
return regNum;
}
int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
+ void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
+
MachineBasicBlock *getMachineBasicBlock() const {
assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
return MBB;
return *SymbolName;
}
- bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
- bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
- bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
- bool opHiBits32 () const { return flags & HIFLAG32; }
- bool opLoBits32 () const { return flags & LOFLAG32; }
- bool opHiBits64 () const { return flags & HIFLAG64; }
- bool opLoBits64 () const { return flags & LOFLAG64; }
+ bool isUse () const { return flags & USEFLAG; }
+ MachineOperand& setUse () { flags |= USEFLAG; return *this; }
+ bool isDef () const { return flags & DEFFLAG; }
+ MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
+ bool isHiBits32 () const { return flags & HIFLAG32; }
+ bool isLoBits32 () const { return flags & LOFLAG32; }
+ bool isHiBits64 () const { return flags & HIFLAG64; }
+ bool isLoBits64 () const { return flags & LOFLAG64; }
// used to check if a machine register has been allocated to this operand
bool hasAllocatedReg() const {
unsigned getReg() const {
return getAllocatedRegNum();
}
+ void setReg(unsigned Reg) {
+ assert(hasAllocatedReg() && "This operand cannot have a register number!");
+ regNum = Reg;
+ }
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
inline VTy operator->() const { return operator*(); }
- inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
- inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
- inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
+ inline bool isUse() const { return MI->getOperand(i).isUse(); }
+ inline bool isDef() const { return MI->getOperand(i).isDef(); }
inline _Self& operator++() { i++; skipToNextVal(); return *this; }
inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
void PrintMachineInstructions(const Function *F);
+} // End llvm namespace
+
#endif
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