-// $Id$ -*-c++-*-
-//***************************************************************************
-// File:
-// MachineInstr.h
-//
-// Purpose:
-//
-//
-// Strategy:
-//
-// History:
-// 7/2/01 - Vikram Adve - Created
-//**************************************************************************/
+//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
+//
+// This file contains the declaration of the MachineInstr class, which is the
+// basic representation for all target dependant machine instructions used by
+// the back end.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H
-#include "llvm/CodeGen/InstrForest.h"
-#include "llvm/Tools/DataTypes.h"
-#include "llvm/Support/Unique.h"
-#include "llvm/CodeGen/TargetMachine.h"
+#include "llvm/Annotation.h"
+#include "Support/iterator"
+#include "Support/NonCopyable.h"
+#include <vector>
+class Value;
+class Function;
+class MachineBasicBlock;
+class TargetMachine;
+
+typedef int MachineOpCode;
+
+/// MOTy - MachineOperandType - This namespace contains an enum that describes
+/// how the machine operand is used by the instruction: is it read, defined, or
+/// both? Note that the MachineInstr/Operator class currently uses bool
+/// arguments to represent this information instead of an enum. Eventually this
+/// should change over to use this _easier to read_ representation instead.
+///
+namespace MOTy {
+ enum UseType {
+ Use, /// This machine operand is only read by the instruction
+ Def, /// This machine operand is only written by the instruction
+ UseAndDef /// This machine operand is read AND written
+ };
+}
//---------------------------------------------------------------------------
// class MachineOperand
//---------------------------------------------------------------------------
class MachineOperand {
-public:
- friend ostream& operator<<(ostream& os, const MachineOperand& mop);
-
public:
enum MachineOperandType {
- MO_Register,
+ MO_VirtualRegister, // virtual register for *value
+ MO_MachineRegister, // pre-assigned machine register `regNum'
MO_CCRegister,
MO_SignExtendedImmed,
MO_UnextendedImmed,
MO_PCRelativeDisp,
};
- enum VirtualRegisterType {
- MO_VirtualReg, // virtual register for *value
- MO_MachineReg // pre-assigned machine register `regNum'
- };
-
- MachineOperandType machineOperandType;
-
- VirtualRegisterType vregType;
+private:
+ // Bit fields of the flags variable used for different operand properties
+ static const char DEFFLAG = 0x1; // this is a def of the operand
+ static const char DEFUSEFLAG = 0x2; // this is both a def and a use
+ static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
+ static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
+ static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
+ static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
- Value* value; // BasicBlockVal for a label operand.
+private:
+ union {
+ Value* value; // BasicBlockVal for a label operand.
// ConstantVal for a non-address immediate.
- // Virtual register for a register operand.
-
- unsigned int regNum; // register number for an explicit register
-
- int64_t immedVal; // constant value for an explicit constant
-
- /*ctor*/ MachineOperand ();
- /*ctor*/ MachineOperand (MachineOperandType operandType,
- Value* _val);
- /*copy ctor*/ MachineOperand (const MachineOperand&);
- /*dtor*/ ~MachineOperand () {}
+ // Virtual register for an SSA operand,
+ // including hidden operands required for
+ // the generated machine code.
+ int64_t immedVal; // constant value for an explicit constant
+ };
+
+ MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
+ char flags; // see bit field definitions above
+ int regNum; // register number for an explicit register
+ // will be set for a value after reg allocation
+private:
+ MachineOperand()
+ : immedVal(0),
+ opType(MO_VirtualRegister),
+ flags(0),
+ regNum(-1) {}
+
+ MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
+ : immedVal(ImmVal),
+ opType(OpTy),
+ flags(0),
+ regNum(-1) {}
+
+ MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
+ : immedVal(0),
+ opType(OpTy),
+ regNum(Reg) {
+ switch (UseTy) {
+ case MOTy::Use: flags = 0; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ default: assert(0 && "Invalid value for UseTy!");
+ }
+ }
+
+ MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy)
+ : value(V), opType(OpTy), regNum(-1) {
+ switch (UseTy) {
+ case MOTy::Use: flags = 0; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ default: assert(0 && "Invalid value for UseTy!");
+ }
+ }
+
+public:
+ MachineOperand(const MachineOperand &M)
+ : immedVal(M.immedVal),
+ opType(M.opType),
+ flags(M.flags),
+ regNum(M.regNum) {}
+
+ ~MachineOperand() {}
- // These functions are provided so that a vector of operands can be
- // statically allocated and individual ones can be initialized later.
+ // Accessor methods. Caller is responsible for checking the
+ // operand type before invoking the corresponding accessor.
//
- void Initialize (MachineOperandType operandType,
- Value* _val);
- void InitializeConst (MachineOperandType operandType,
- int64_t intValue);
- void InitializeReg (unsigned int regNum);
-};
+ MachineOperandType getType() const { return opType; }
+ inline Value* getVRegValue () const {
+ assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_PCRelativeDisp);
+ return value;
+ }
+ inline Value* getVRegValueOrNull() const {
+ return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_PCRelativeDisp)? value : NULL;
+ }
+ inline int getMachineRegNum() const {
+ assert(opType == MO_MachineRegister);
+ return regNum;
+ }
+ inline int64_t getImmedValue () const {
+ assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
+ return immedVal;
+ }
+ bool opIsDef () const { return flags & DEFFLAG; }
+ bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
+ bool opHiBits32 () const { return flags & HIFLAG32; }
+ bool opLoBits32 () const { return flags & LOFLAG32; }
+ bool opHiBits64 () const { return flags & HIFLAG64; }
+ bool opLoBits64 () const { return flags & LOFLAG64; }
+
+ // used to check if a machine register has been allocated to this operand
+ inline bool hasAllocatedReg() const {
+ return (regNum >= 0 &&
+ (opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_MachineRegister));
+ }
-inline
-MachineOperand::MachineOperand()
- : machineOperandType(MO_Register),
- vregType(MO_VirtualReg),
- value(NULL),
- regNum(0),
- immedVal(0)
-{}
-
-inline
-MachineOperand::MachineOperand(MachineOperandType operandType,
- Value* _val)
- : machineOperandType(operandType),
- vregType(MO_VirtualReg),
- value(_val),
- regNum(0),
- immedVal(0)
-{}
-
-inline
-MachineOperand::MachineOperand(const MachineOperand& mo)
- : machineOperandType(mo.machineOperandType),
- vregType(mo.vregType),
- value(mo.value),
- regNum(mo.regNum),
- immedVal(mo.immedVal)
-{
-}
+ // used to get the reg number if when one is allocated
+ inline int getAllocatedRegNum() const {
+ assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_MachineRegister);
+ return regNum;
+ }
-inline void
-MachineOperand::Initialize(MachineOperandType operandType,
- Value* _val)
-{
- machineOperandType = operandType;
- value = _val;
-}
+ inline unsigned getReg() const {
+ assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!");
+ return regNum;
+ }
+
+ friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
-inline void
-MachineOperand::InitializeConst(MachineOperandType operandType,
- int64_t intValue)
-{
- machineOperandType = operandType;
- value = NULL;
- immedVal = intValue;
-}
+private:
-inline void
-MachineOperand::InitializeReg(unsigned int _regNum)
-{
- machineOperandType = MO_Register;
- vregType = MO_MachineReg;
- value = NULL;
- regNum = _regNum;
-}
+ // Construction methods needed for fine-grain control.
+ // These must be accessed via coresponding methods in MachineInstr.
+ void markHi32() { flags |= HIFLAG32; }
+ void markLo32() { flags |= LOFLAG32; }
+ void markHi64() { flags |= HIFLAG64; }
+ void markLo64() { flags |= LOFLAG64; }
+
+ // Replaces the Value with its corresponding physical register after
+ // register allocation is complete
+ void setRegForValue(int reg) {
+ assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_MachineRegister);
+ regNum = reg;
+ }
+
+ friend class MachineInstr;
+};
//---------------------------------------------------------------------------
//
// MachineOpCode must be an enum, defined separately for each target.
// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
-// The array MachineInstrInfo TargetMachineInstrInfo[] objects
-// (indexed by opCode) provides information about each target instruction.
//
-// opCodeMask is used to record variants of an instruction.
-// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
-// ANNUL: if 1: Annul delay slot instruction.
-// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
-// Instead of creating 4 different opcodes for BNZ, we create a single
-// opcode and set bits in opCodeMask for each of these flags.
+// There are 2 kinds of operands:
+//
+// (1) Explicit operands of the machine instruction in vector operands[]
+//
+// (2) "Implicit operands" are values implicitly used or defined by the
+// machine instruction, such as arguments to a CALL, return value of
+// a CALL (if any), and return value of a RETURN.
//---------------------------------------------------------------------------
-class MachineInstr : public Unique {
-private:
- MachineOpCode opCode;
- OpCodeMask opCodeMask; // extra bits for variants of an opcode
- vector<MachineOperand> operands; // operand 0 is the result
-
+class MachineInstr: public NonCopyable { // Disable copy operations
+
+ MachineOpCode opCode; // the opcode
+ std::vector<MachineOperand> operands; // the operands
+ unsigned numImplicitRefs; // number of implicit operands
+
+ MachineOperand& getImplicitOp(unsigned i) {
+ assert(i < numImplicitRefs && "implicit ref# out of range!");
+ return operands[i + operands.size() - numImplicitRefs];
+ }
+ const MachineOperand& getImplicitOp(unsigned i) const {
+ assert(i < numImplicitRefs && "implicit ref# out of range!");
+ return operands[i + operands.size() - numImplicitRefs];
+ }
+
+ // regsUsed - all machine registers used for this instruction, including regs
+ // used to save values across the instruction. This is a bitset of registers.
+ std::vector<bool> regsUsed;
+
+ // OperandComplete - Return true if it's illegal to add a new operand
+ bool OperandsComplete() const;
+
public:
- /*ctor*/ MachineInstr (MachineOpCode _opCode,
- OpCodeMask _opCodeMask = 0x0);
-
- /*dtor*/ ~MachineInstr ();
+ MachineInstr(MachineOpCode Opcode);
+ MachineInstr(MachineOpCode Opcode, unsigned numOperands);
+
+ /// MachineInstr ctor - This constructor only does a _reserve_ of the
+ /// operands, not a resize for them. It is expected that if you use this that
+ /// you call add* methods below to fill up the operands, instead of the Set
+ /// methods. Eventually, the "resizing" ctors will be phased out.
+ ///
+ MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
+
+ /// MachineInstr ctor - Work exactly the same as the ctor above, except that
+ /// the MachineInstr is created and added to the end of the specified basic
+ /// block.
+ ///
+ MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
- const MachineOpCode getOpCode () const;
+
+ /// replace - Support to rewrite a machine instruction in place: for now,
+ /// simply replace() and then set new operands with Set.*Operand methods
+ /// below.
+ ///
+ void replace(MachineOpCode Opcode, unsigned numOperands);
- unsigned int getNumOperands () const;
+ // The opcode.
+ //
+ const MachineOpCode getOpcode() const { return opCode; }
+ const MachineOpCode getOpCode() const { return opCode; }
+
+ //
+ // Information about explicit operands of the instruction
+ //
+ unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
- const MachineOperand& getOperand (unsigned int i) const;
+ const MachineOperand& getOperand(unsigned i) const {
+ assert(i < getNumOperands() && "getOperand() out of range!");
+ return operands[i];
+ }
+ MachineOperand& getOperand(unsigned i) {
+ assert(i < getNumOperands() && "getOperand() out of range!");
+ return operands[i];
+ }
+
+ MachineOperand::MachineOperandType getOperandType(unsigned i) const {
+ return getOperand(i).getType();
+ }
+
+ bool operandIsDefined(unsigned i) const {
+ return getOperand(i).opIsDef();
+ }
+
+ bool operandIsDefinedAndUsed(unsigned i) const {
+ return getOperand(i).opIsDefAndUse();
+ }
+
+ //
+ // Information about implicit operands of the instruction
+ //
+ unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
- void dump (unsigned int indent = 0);
+ const Value* getImplicitRef(unsigned i) const {
+ return getImplicitOp(i).getVRegValue();
+ }
+ Value* getImplicitRef(unsigned i) {
+ return getImplicitOp(i).getVRegValue();
+ }
+
+ bool implicitRefIsDefined(unsigned i) const {
+ return getImplicitOp(i).opIsDef();
+ }
+ bool implicitRefIsDefinedAndUsed(unsigned i) const {
+ return getImplicitOp(i).opIsDefAndUse();
+ }
+ inline void addImplicitRef (Value* V,
+ bool isDef=false,bool isDefAndUse=false);
+ inline void setImplicitRef (unsigned i, Value* V,
+ bool isDef=false, bool isDefAndUse=false);
+
+ //
+ // Information about registers used in this instruction
+ //
+ const std::vector<bool> &getRegsUsed() const { return regsUsed; }
-public:
- friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
+ // insertUsedReg - Add a register to the Used registers set...
+ void insertUsedReg(unsigned Reg) {
+ if (Reg >= regsUsed.size())
+ regsUsed.resize(Reg+1);
+ regsUsed[Reg] = true;
+ }
+
+ //
+ // Debugging support
+ //
+ void print(std::ostream &OS, const TargetMachine &TM) const;
+ void dump() const;
+ friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
+
+ //
+ // Define iterators to access the Value operands of the Machine Instruction.
+ // Note that these iterators only enumerate the explicit operands.
+ // begin() and end() are defined to produce these iterators...
+ //
+ template<class _MI, class _V> class ValOpIterator;
+ typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
+ typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
-public:
// Access to set the operands when building the machine instruction
- void SetMachineOperand(unsigned int i,
- MachineOperand::MachineOperandType operandType,
- Value* _val);
- void SetMachineOperand(unsigned int i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue);
- void SetMachineOperand(unsigned int i,
- unsigned int regNum);
-};
+ //
+ void SetMachineOperandVal (unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ Value* V,
+ bool isDef=false,
+ bool isDefAndUse=false);
+
+ void SetMachineOperandConst (unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ int64_t intValue);
+
+ void SetMachineOperandReg (unsigned i,
+ int regNum,
+ bool isDef=false);
+
+ //===--------------------------------------------------------------------===//
+ // Accessors to add operands when building up machine instructions
+ //
-inline const MachineOpCode
-MachineInstr::getOpCode() const
-{
- return opCode;
-}
+ /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
+ /// operands list...
+ ///
+ void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
+ !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
+ }
-inline unsigned int
-MachineInstr::getNumOperands() const
-{
- assert(operands.size() == TargetMachineInstrInfo[opCode].numOperands);
- return operands.size();
-}
+ void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
+ UTy));
+ }
-inline const MachineOperand&
-MachineInstr::getOperand(unsigned int i) const
-{
- return operands[i];
-}
+ /// addRegOperand - Add a symbolic virtual register reference...
+ ///
+ void addRegOperand(int reg, bool isDef) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ isDef ? MOTy::Def : MOTy::Use));
+ }
+ /// addRegOperand - Add a symbolic virtual register reference...
+ ///
+ void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ UTy));
+ }
-//---------------------------------------------------------------------------
-// class MachineInstructionsForVMInstr
-//
-// Purpose:
-// Representation of the sequence of machine instructions created
-// for a single VM instruction. Additionally records any temporary
-// "values" used as intermediate values in this sequence.
-// Note that such values should be treated as pure SSA values with
-// no interpretation of their operands (i.e., as a TmpInstruction object
-// which actually represents such a value).
-//
-//---------------------------------------------------------------------------
+ /// addPCDispOperand - Add a PC relative displacement operand to the MI
+ ///
+ void addPCDispOperand(Value *V) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
+ MOTy::Use));
+ }
-class MachineCodeForVMInstr: public vector<MachineInstr*>
-{
-private:
- vector<Value*> tempVec;
-
-public:
- /*ctor*/ MachineCodeForVMInstr () {}
- /*ctor*/ ~MachineCodeForVMInstr ();
+ /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
+ ///
+ void addMachineRegOperand(int reg, bool isDef) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
+ isDef ? MOTy::Def : MOTy::Use));
+ insertUsedReg(reg);
+ }
+
+ /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
+ ///
+ void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
+ UTy));
+ insertUsedReg(reg);
+ }
+
+ /// addZeroExtImmOperand - Add a zero extended constant argument to the
+ /// machine instruction.
+ ///
+ void addZeroExtImmOperand(int64_t intValue) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(intValue,
+ MachineOperand::MO_UnextendedImmed));
+ }
+
+ /// addSignExtImmOperand - Add a zero extended constant argument to the
+ /// machine instruction.
+ ///
+ void addSignExtImmOperand(int64_t intValue) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(intValue,
+ MachineOperand::MO_SignExtendedImmed));
+ }
+
+
+ unsigned substituteValue(const Value* oldVal, Value* newVal,
+ bool defsOnly = true);
+
+ void setOperandHi32(unsigned i) { operands[i].markHi32(); }
+ void setOperandLo32(unsigned i) { operands[i].markLo32(); }
+ void setOperandHi64(unsigned i) { operands[i].markHi64(); }
+ void setOperandLo64(unsigned i) { operands[i].markLo64(); }
- const vector<Value*>&
- getTempValues () const { return tempVec; }
- void addTempValue (Value* val)
- { tempVec.push_back(val); }
+ // SetRegForOperand - Replaces the Value for the operand with its allocated
+ // physical register after register allocation is complete.
+ //
+ void SetRegForOperand(unsigned i, int regNum);
- // dropAllReferences() - This function drops all references within
- // temporary (hidden) instructions created in implementing the original
- // VM intruction. This ensures there are no remaining "uses" within
- // these hidden instructions, before the values of a method are freed.
//
- // Make this inline because it has to be called from class Instruction
- // and inlining it avoids a serious circurality in link order.
- inline void dropAllReferences() {
- for (unsigned i=0, N=tempVec.size(); i < N; i++)
- if (tempVec[i]->getValueType() == Value::InstructionVal)
- ((Instruction*) tempVec[i])->dropAllReferences();
+ // Iterator to enumerate machine operands.
+ //
+ template<class MITy, class VTy>
+ class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
+ unsigned i;
+ MITy MI;
+
+ void skipToNextVal() {
+ while (i < MI->getNumOperands() &&
+ !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
+ MI->getOperandType(i) == MachineOperand::MO_CCRegister)
+ && MI->getOperand(i).getVRegValue() != 0))
+ ++i;
+ }
+
+ inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
+ skipToNextVal();
+ }
+
+ public:
+ typedef ValOpIterator<MITy, VTy> _Self;
+
+ inline VTy operator*() const {
+ return MI->getOperand(i).getVRegValue();
+ }
+
+ const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
+ MachineOperand &getMachineOperand() { return MI->getOperand(i);}
+
+ inline VTy operator->() const { return operator*(); }
+
+ inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
+ inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
+
+ inline _Self& operator++() { i++; skipToNextVal(); return *this; }
+ inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
+
+ inline bool operator==(const _Self &y) const {
+ return i == y.i;
+ }
+ inline bool operator!=(const _Self &y) const {
+ return !operator==(y);
+ }
+
+ static _Self begin(MITy MI) {
+ return _Self(MI, 0);
+ }
+ static _Self end(MITy MI) {
+ return _Self(MI, MI->getNumOperands());
+ }
+ };
+
+ // define begin() and end()
+ val_op_iterator begin() { return val_op_iterator::begin(this); }
+ val_op_iterator end() { return val_op_iterator::end(this); }
+
+ const_val_op_iterator begin() const {
+ return const_val_op_iterator::begin(this);
+ }
+ const_val_op_iterator end() const {
+ return const_val_op_iterator::end(this);
}
};
-inline
-MachineCodeForVMInstr::~MachineCodeForVMInstr()
+
+// Define here to enable inlining of the functions used.
+//
+void MachineInstr::addImplicitRef(Value* V,
+ bool isDef,
+ bool isDefAndUse)
{
- // Free the Value objects created to hold intermediate values
- for (unsigned i=0, N=tempVec.size(); i < N; i++)
- delete tempVec[i];
-
- // Free the MachineInstr objects allocated, if any.
- for (unsigned i=0, N=this->size(); i < N; i++)
- delete (*this)[i];
+ ++numImplicitRefs;
+ addRegOperand(V, isDef, isDefAndUse);
}
+void MachineInstr::setImplicitRef(unsigned i,
+ Value* V,
+ bool isDef,
+ bool isDefAndUse)
+{
+ assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
+ SetMachineOperandVal(i + getNumOperands(),
+ MachineOperand::MO_VirtualRegister,
+ V, isDef, isDefAndUse);
+}
+
+
//---------------------------------------------------------------------------
-// Target-independent utility routines for creating machine instructions
+// Debugging Support
//---------------------------------------------------------------------------
+std::ostream& operator<< (std::ostream& os,
+ const MachineInstr& minstr);
-//------------------------------------------------------------------------
-// Function Set2OperandsFromInstr
-// Function Set3OperandsFromInstr
-//
-// For the common case of 2- and 3-operand arithmetic/logical instructions,
-// set the m/c instr. operands directly from the VM instruction's operands.
-// Check whether the first or second operand is 0 and can use a dedicated
-// "0" register.
-// Check whether the second operand should use an immediate field or register.
-// (First and third operands are never immediates for such instructions.)
-//
-// Arguments:
-// canDiscardResult: Specifies that the result operand can be discarded
-// by using the dedicated "0"
-//
-// op1position, op2position and resultPosition: Specify in which position
-// in the machine instruction the 3 operands (arg1, arg2
-// and result) should go.
-//
-// RETURN VALUE: unsigned int flags, where
-// flags & 0x01 => operand 1 is constant and needs a register
-// flags & 0x02 => operand 2 is constant and needs a register
-//------------------------------------------------------------------------
-
-void Set2OperandsFromInstr (MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& targetMachine,
- bool canDiscardResult = false,
- int op1Position = 0,
- int resultPosition = 1);
-
-void Set3OperandsFromInstr (MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& targetMachine,
- bool canDiscardResult = false,
- int op1Position = 0,
- int op2Position = 1,
- int resultPosition = 2);
-
-MachineOperand::MachineOperandType
- ChooseRegOrImmed(Value* val,
- MachineOpCode opCode,
- const TargetMachine& targetMachine,
- bool canUseImmed,
- MachineOperand::VirtualRegisterType& getVRegType,
- unsigned int& getMachineRegNum,
- int64_t& getImmedValue);
-
-ostream& operator<<(ostream& os, const MachineInstr& minstr);
-
-
-ostream& operator<<(ostream& os, const MachineOperand& mop);
+std::ostream& operator<< (std::ostream& os,
+ const MachineOperand& mop);
-
-//**************************************************************************/
+void PrintMachineInstructions (const Function *F);
#endif