#include <vector>
class Value;
class Function;
+class MachineBasicBlock;
+class TargetMachine;
typedef int MachineOpCode;
-typedef int OpCodeMask;
+
+/// MOTy - MachineOperandType - This namespace contains an enum that describes
+/// how the machine operand is used by the instruction: is it read, defined, or
+/// both? Note that the MachineInstr/Operator class currently uses bool
+/// arguments to represent this information instead of an enum. Eventually this
+/// should change over to use this _easier to read_ representation instead.
+///
+namespace MOTy {
+ enum UseType {
+ Use, /// This machine operand is only read by the instruction
+ Def, /// This machine operand is only written by the instruction
+ UseAndDef /// This machine operand is read AND written
+ };
+}
//---------------------------------------------------------------------------
// class MachineOperand
// will be set for a value after reg allocation
private:
MachineOperand()
- : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1) {}
+ : immedVal(0),
+ opType(MO_VirtualRegister),
+ flags(0),
+ regNum(-1) {}
+
MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
- : immedVal(ImmVal), opType(OpTy), flags(0), regNum(-1) {}
- MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
- : immedVal(0), opType(OpTy), flags(isDef ? DEFFLAG : 0), regNum(Reg) {}
- MachineOperand(Value *V, MachineOperandType OpTy,
- bool isDef = false, bool isDNU = false)
+ : immedVal(ImmVal),
+ opType(OpTy),
+ flags(0),
+ regNum(-1) {}
+
+ MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
+ : immedVal(0),
+ opType(OpTy),
+ regNum(Reg) {
+ switch (UseTy) {
+ case MOTy::Use: flags = 0; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ default: assert(0 && "Invalid value for UseTy!");
+ }
+ }
+
+ MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy)
: value(V), opType(OpTy), regNum(-1) {
- flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
+ switch (UseTy) {
+ case MOTy::Use: flags = 0; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ default: assert(0 && "Invalid value for UseTy!");
+ }
}
public:
MachineOperand(const MachineOperand &M)
- : immedVal(M.immedVal), opType(M.opType), flags(M.flags), regNum(M.regNum) {
- }
+ : immedVal(M.immedVal),
+ opType(M.opType),
+ flags(M.flags),
+ regNum(M.regNum) {}
+
~MachineOperand() {}
// Accessor methods. Caller is responsible for checking the
return regNum;
}
+ inline unsigned getReg() const {
+ assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!");
+ return regNum;
+ }
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
// Construction methods needed for fine-grain control.
// These must be accessed via coresponding methods in MachineInstr.
- void markDef() { flags |= DEFFLAG; }
- void markDefAndUse() { flags |= DEFUSEFLAG; }
void markHi32() { flags |= HIFLAG32; }
void markLo32() { flags |= LOFLAG32; }
void markHi64() { flags |= HIFLAG64; }
// MachineOpCode must be an enum, defined separately for each target.
// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
//
-// opCodeMask is used to record variants of an instruction.
-// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
-// ANNUL: if 1: Annul delay slot instruction.
-// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
-// Instead of creating 4 different opcodes for BNZ, we create a single
-// opcode and set bits in opCodeMask for each of these flags.
-//
// There are 2 kinds of operands:
//
// (1) Explicit operands of the machine instruction in vector operands[]
// a CALL (if any), and return value of a RETURN.
//---------------------------------------------------------------------------
-class MachineInstr : public Annotable, // MachineInstrs are annotable
- public NonCopyable { // Disable copy operations
+class MachineInstr: public NonCopyable { // Disable copy operations
+
MachineOpCode opCode; // the opcode
- OpCodeMask opCodeMask; // extra bits for variants of an opcode
std::vector<MachineOperand> operands; // the operands
+ unsigned numImplicitRefs; // number of implicit operands
- struct ImplicitRef {
- Value *Val;
- bool isDef, isDefAndUse;
-
- ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
- };
-
- // implicitRefs - Values implicitly referenced by this machine instruction
- // (eg, call args)
- std::vector<ImplicitRef> implicitRefs;
+ MachineOperand& getImplicitOp(unsigned i) {
+ assert(i < numImplicitRefs && "implicit ref# out of range!");
+ return operands[i + operands.size() - numImplicitRefs];
+ }
+ const MachineOperand& getImplicitOp(unsigned i) const {
+ assert(i < numImplicitRefs && "implicit ref# out of range!");
+ return operands[i + operands.size() - numImplicitRefs];
+ }
// regsUsed - all machine registers used for this instruction, including regs
// used to save values across the instruction. This is a bitset of registers.
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
+
public:
MachineInstr(MachineOpCode Opcode);
MachineInstr(MachineOpCode Opcode, unsigned numOperands);
/// MachineInstr ctor - This constructor only does a _reserve_ of the
/// operands, not a resize for them. It is expected that if you use this that
/// you call add* methods below to fill up the operands, instead of the Set
- /// methods.
+ /// methods. Eventually, the "resizing" ctors will be phased out.
///
MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
- //
- // Support to rewrite a machine instruction in place: for now, simply
- // replace() and then set new operands with Set.*Operand methods below.
- //
- void replace(MachineOpCode Opcode, unsigned numOperands,
- OpCodeMask Mask = 0x0);
+ /// MachineInstr ctor - Work exactly the same as the ctor above, except that
+ /// the MachineInstr is created and added to the end of the specified basic
+ /// block.
+ ///
+ MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
+
+
+ /// replace - Support to rewrite a machine instruction in place: for now,
+ /// simply replace() and then set new operands with Set.*Operand methods
+ /// below.
+ ///
+ void replace(MachineOpCode Opcode, unsigned numOperands);
- //
// The opcode.
//
+ const MachineOpCode getOpcode() const { return opCode; }
const MachineOpCode getOpCode() const { return opCode; }
//
// Information about explicit operands of the instruction
//
- unsigned getNumOperands() const { return operands.size(); }
+ unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
const MachineOperand& getOperand(unsigned i) const {
- assert(i < operands.size() && "getOperand() out of range!");
+ assert(i < getNumOperands() && "getOperand() out of range!");
return operands[i];
}
MachineOperand& getOperand(unsigned i) {
- assert(i < operands.size() && "getOperand() out of range!");
+ assert(i < getNumOperands() && "getOperand() out of range!");
return operands[i];
}
bool operandIsDefinedAndUsed(unsigned i) const {
return getOperand(i).opIsDefAndUse();
}
-
+
//
// Information about implicit operands of the instruction
//
- unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
+ unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
const Value* getImplicitRef(unsigned i) const {
- assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
- return implicitRefs[i].Val;
+ return getImplicitOp(i).getVRegValue();
}
Value* getImplicitRef(unsigned i) {
- assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
- return implicitRefs[i].Val;
+ return getImplicitOp(i).getVRegValue();
}
bool implicitRefIsDefined(unsigned i) const {
- assert(i < implicitRefs.size() && "implicitRefIsDefined() out of range!");
- return implicitRefs[i].isDef;
+ return getImplicitOp(i).opIsDef();
}
bool implicitRefIsDefinedAndUsed(unsigned i) const {
- assert(i < implicitRefs.size() && "implicitRefIsDef&Used() out of range!");
- return implicitRefs[i].isDefAndUse;
- }
-
- void addImplicitRef(Value* V, bool isDef=false, bool isDefAndUse=false) {
- implicitRefs.push_back(ImplicitRef(V, isDef, isDefAndUse));
- }
-
- void setImplicitRef(unsigned i, Value* V, bool isDef=false,
- bool isDefAndUse=false) {
- assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
- implicitRefs[i] = ImplicitRef(V, isDef, isDefAndUse);
+ return getImplicitOp(i).opIsDefAndUse();
}
-
+ inline void addImplicitRef (Value* V,
+ bool isDef=false,bool isDefAndUse=false);
+ inline void setImplicitRef (unsigned i, Value* V,
+ bool isDef=false, bool isDefAndUse=false);
+
//
// Information about registers used in this instruction
//
//
// Debugging support
- //
+ //
+ void print(std::ostream &OS, const TargetMachine &TM) const;
void dump() const;
friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
//
// Define iterators to access the Value operands of the Machine Instruction.
+ // Note that these iterators only enumerate the explicit operands.
// begin() and end() are defined to produce these iterators...
//
template<class _MI, class _V> class ValOpIterator;
typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
-
// Access to set the operands when building the machine instruction
//
- void SetMachineOperandVal(unsigned i,
- MachineOperand::MachineOperandType operandType,
- Value* V, bool isDef=false, bool isDefAndUse=false);
- void SetMachineOperandConst(unsigned i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue);
- void SetMachineOperandReg(unsigned i, int regNum, bool isDef=false);
+ void SetMachineOperandVal (unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ Value* V,
+ bool isDef=false,
+ bool isDefAndUse=false);
+
+ void SetMachineOperandConst (unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ int64_t intValue);
+
+ void SetMachineOperandReg (unsigned i,
+ int regNum,
+ bool isDef=false);
//===--------------------------------------------------------------------===//
// Accessors to add operands when building up machine instructions
/// addRegOperand - Add a MO_VirtualRegister operand to the end of the
/// operands list...
///
- void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
+ void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
- isDef, isDefAndUse));
+ !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
+ }
+
+ void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
+ UTy));
+ }
+
+ /// addRegOperand - Add a symbolic virtual register reference...
+ ///
+ void addRegOperand(int reg, bool isDef) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ isDef ? MOTy::Def : MOTy::Use));
}
/// addRegOperand - Add a symbolic virtual register reference...
///
- void addRegOperand(int reg) {
+ void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ UTy));
}
/// addPCDispOperand - Add a PC relative displacement operand to the MI
void addPCDispOperand(Value *V) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
- operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
+ operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
+ MOTy::Use));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
///
- void addMachineRegOperand(int reg, bool isDef=false) {
+ void addMachineRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
- isDef));
+ isDef ? MOTy::Def : MOTy::Use));
+ insertUsedReg(reg);
+ }
+
+ /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
+ ///
+ void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
+ UTy));
insertUsedReg(reg);
}
void skipToNextVal() {
while (i < MI->getNumOperands() &&
- !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
- MI->getOperandType(i) == MachineOperand::MO_CCRegister)
- && MI->getOperand(i).getVRegValue() != 0))
+ !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
+ MI->getOperandType(i) == MachineOperand::MO_CCRegister)
+ && MI->getOperand(i).getVRegValue() != 0))
++i;
}
}
};
+
+// Define here to enable inlining of the functions used.
+//
+void MachineInstr::addImplicitRef(Value* V,
+ bool isDef,
+ bool isDefAndUse)
+{
+ ++numImplicitRefs;
+ addRegOperand(V, isDef, isDefAndUse);
+}
+
+void MachineInstr::setImplicitRef(unsigned i,
+ Value* V,
+ bool isDef,
+ bool isDefAndUse)
+{
+ assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
+ SetMachineOperandVal(i + getNumOperands(),
+ MachineOperand::MO_VirtualRegister,
+ V, isDef, isDefAndUse);
+}
+
+
//---------------------------------------------------------------------------
// Debugging Support
//---------------------------------------------------------------------------
-std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
+std::ostream& operator<< (std::ostream& os,
+ const MachineInstr& minstr);
-std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
+std::ostream& operator<< (std::ostream& os,
+ const MachineOperand& mop);
-void PrintMachineInstructions(const Function *F);
+void PrintMachineInstructions (const Function *F);
#endif
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