#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H
-#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Annotation.h"
-#include <iterator>
-class Instruction;
+#include "Support/iterator"
+#include "Support/NonCopyable.h"
+#include <vector>
+class Value;
+class Function;
+class MachineBasicBlock;
+class TargetMachine;
+
+typedef int MachineOpCode;
+
+/// MOTy - MachineOperandType - This namespace contains an enum that describes
+/// how the machine operand is used by the instruction: is it read, defined, or
+/// both? Note that the MachineInstr/Operator class currently uses bool
+/// arguments to represent this information instead of an enum. Eventually this
+/// should change over to use this _easier to read_ representation instead.
+///
+namespace MOTy {
+ enum UseType {
+ Use, /// This machine operand is only read by the instruction
+ Def, /// This machine operand is only written by the instruction
+ UseAndDef /// This machine operand is read AND written
+ };
+}
//---------------------------------------------------------------------------
// class MachineOperand
//
//---------------------------------------------------------------------------
-
class MachineOperand {
public:
enum MachineOperandType {
};
private:
- MachineOperandType opType;
+ // Bit fields of the flags variable used for different operand properties
+ static const char DEFFLAG = 0x1; // this is a def of the operand
+ static const char DEFUSEFLAG = 0x2; // this is both a def and a use
+ static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
+ static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
+ static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
+ static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
+private:
union {
Value* value; // BasicBlockVal for a label operand.
// ConstantVal for a non-address immediate.
int64_t immedVal; // constant value for an explicit constant
};
+ MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
+ char flags; // see bit field definitions above
int regNum; // register number for an explicit register
// will be set for a value after reg allocation
- bool isDef; // is this a defition for the value
-
+private:
+ MachineOperand()
+ : immedVal(0),
+ opType(MO_VirtualRegister),
+ flags(0),
+ regNum(-1) {}
+
+ MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
+ : immedVal(ImmVal),
+ opType(OpTy),
+ flags(0),
+ regNum(-1) {}
+
+ MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
+ : immedVal(0),
+ opType(OpTy),
+ regNum(Reg) {
+ switch (UseTy) {
+ case MOTy::Use: flags = 0; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ default: assert(0 && "Invalid value for UseTy!");
+ }
+ }
+
+ MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy)
+ : value(V), opType(OpTy), regNum(-1) {
+ switch (UseTy) {
+ case MOTy::Use: flags = 0; break;
+ case MOTy::Def: flags = DEFFLAG; break;
+ case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
+ default: assert(0 && "Invalid value for UseTy!");
+ }
+ }
+
public:
- /*ctor*/ MachineOperand ();
- /*ctor*/ MachineOperand (MachineOperandType operandType,
- Value* _val);
- /*copy ctor*/ MachineOperand (const MachineOperand&);
- /*dtor*/ ~MachineOperand () {}
+ MachineOperand(const MachineOperand &M)
+ : immedVal(M.immedVal),
+ opType(M.opType),
+ flags(M.flags),
+ regNum(M.regNum) {}
+
+ ~MachineOperand() {}
// Accessor methods. Caller is responsible for checking the
// operand type before invoking the corresponding accessor.
//
- inline MachineOperandType getOperandType() const {
- return opType;
- }
+ MachineOperandType getType() const { return opType; }
+
inline Value* getVRegValue () const {
assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
opType == MO_PCRelativeDisp);
return value;
}
+ inline Value* getVRegValueOrNull() const {
+ return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_PCRelativeDisp)? value : NULL;
+ }
inline int getMachineRegNum() const {
assert(opType == MO_MachineRegister);
return regNum;
assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
return immedVal;
}
- inline bool opIsDef () const {
- return isDef;
+ bool opIsDef () const { return flags & DEFFLAG; }
+ bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
+ bool opHiBits32 () const { return flags & HIFLAG32; }
+ bool opLoBits32 () const { return flags & LOFLAG32; }
+ bool opHiBits64 () const { return flags & HIFLAG64; }
+ bool opLoBits64 () const { return flags & LOFLAG64; }
+
+ // used to check if a machine register has been allocated to this operand
+ inline bool hasAllocatedReg() const {
+ return (regNum >= 0 &&
+ (opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_MachineRegister));
+ }
+
+ // used to get the reg number if when one is allocated
+ inline int getAllocatedRegNum() const {
+ assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_MachineRegister);
+ return regNum;
}
+
+ inline unsigned getReg() const {
+ assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!");
+ return regNum;
+ }
-public:
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
-
private:
- // These functions are provided so that a vector of operands can be
- // statically allocated and individual ones can be initialized later.
- // Give class MachineInstr gets access to these functions.
- //
- void Initialize (MachineOperandType operandType,
- Value* _val);
- void InitializeConst (MachineOperandType operandType,
- int64_t intValue);
- void InitializeReg (int regNum,
- bool isCCReg);
- friend class MachineInstr;
-
-public:
-
- // replaces the Value with its corresponding physical register after
+ // Construction methods needed for fine-grain control.
+ // These must be accessed via coresponding methods in MachineInstr.
+ void markHi32() { flags |= HIFLAG32; }
+ void markLo32() { flags |= LOFLAG32; }
+ void markHi64() { flags |= HIFLAG64; }
+ void markLo64() { flags |= LOFLAG64; }
+
+ // Replaces the Value with its corresponding physical register after
// register allocation is complete
void setRegForValue(int reg) {
assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
opType == MO_MachineRegister);
regNum = reg;
}
-
- // used to get the reg number if when one is allocted (must be
- // called only after reg alloc)
- inline int getAllocatedRegNum() const {
- assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
- opType == MO_MachineRegister);
- return regNum;
- }
-
-
+
+ friend class MachineInstr;
};
-inline
-MachineOperand::MachineOperand()
- : opType(MO_VirtualRegister),
- immedVal(0),
- regNum(-1),
- isDef(false)
-{}
-
-inline
-MachineOperand::MachineOperand(MachineOperandType operandType,
- Value* _val)
- : opType(operandType),
- immedVal(0),
- regNum(-1),
- isDef(false)
-{}
-
-inline
-MachineOperand::MachineOperand(const MachineOperand& mo)
- : opType(mo.opType),
- isDef(false)
-{
- switch(opType) {
- case MO_VirtualRegister:
- case MO_CCRegister: value = mo.value; break;
- case MO_MachineRegister: regNum = mo.regNum; break;
- case MO_SignExtendedImmed:
- case MO_UnextendedImmed:
- case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
- default: assert(0);
- }
-}
-
-inline void
-MachineOperand::Initialize(MachineOperandType operandType,
- Value* _val)
-{
- opType = operandType;
- value = _val;
- regNum = -1;
-}
-
-inline void
-MachineOperand::InitializeConst(MachineOperandType operandType,
- int64_t intValue)
-{
- opType = operandType;
- value = NULL;
- immedVal = intValue;
- regNum = -1;
-}
-
-inline void
-MachineOperand::InitializeReg(int _regNum, bool isCCReg)
-{
- opType = isCCReg? MO_CCRegister : MO_MachineRegister;
- value = NULL;
- regNum = (int) _regNum;
-}
-
-
//---------------------------------------------------------------------------
// class MachineInstr
//
// MachineOpCode must be an enum, defined separately for each target.
// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
//
-// opCodeMask is used to record variants of an instruction.
-// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
-// ANNUL: if 1: Annul delay slot instruction.
-// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
-// Instead of creating 4 different opcodes for BNZ, we create a single
-// opcode and set bits in opCodeMask for each of these flags.
-//
// There are 2 kinds of operands:
//
// (1) Explicit operands of the machine instruction in vector operands[]
// a CALL (if any), and return value of a RETURN.
//---------------------------------------------------------------------------
-class MachineInstr : public Annotable, // Values are annotable
- public NonCopyableV { // Disable copy operations
- MachineOpCode opCode;
- OpCodeMask opCodeMask; // extra bits for variants of an opcode
- std::vector<MachineOperand> operands;
- std::vector<Value*> implicitRefs; // values implicitly referenced by this
- std::vector<bool> implicitIsDef; // machine instruction (eg, call args)
-
+class MachineInstr: public NonCopyable { // Disable copy operations
+
+ MachineOpCode opCode; // the opcode
+ std::vector<MachineOperand> operands; // the operands
+ unsigned numImplicitRefs; // number of implicit operands
+
+ MachineOperand& getImplicitOp(unsigned i) {
+ assert(i < numImplicitRefs && "implicit ref# out of range!");
+ return operands[i + operands.size() - numImplicitRefs];
+ }
+ const MachineOperand& getImplicitOp(unsigned i) const {
+ assert(i < numImplicitRefs && "implicit ref# out of range!");
+ return operands[i + operands.size() - numImplicitRefs];
+ }
+
+ // regsUsed - all machine registers used for this instruction, including regs
+ // used to save values across the instruction. This is a bitset of registers.
+ std::vector<bool> regsUsed;
+
+ // OperandComplete - Return true if it's illegal to add a new operand
+ bool OperandsComplete() const;
+
public:
- /*ctor*/ MachineInstr (MachineOpCode _opCode,
- OpCodeMask _opCodeMask = 0x0);
- /*ctor*/ MachineInstr (MachineOpCode _opCode,
- unsigned numOperands,
- OpCodeMask _opCodeMask = 0x0);
- inline ~MachineInstr () {}
- const MachineOpCode getOpCode () const { return opCode; }
+ MachineInstr(MachineOpCode Opcode);
+ MachineInstr(MachineOpCode Opcode, unsigned numOperands);
+
+ /// MachineInstr ctor - This constructor only does a _reserve_ of the
+ /// operands, not a resize for them. It is expected that if you use this that
+ /// you call add* methods below to fill up the operands, instead of the Set
+ /// methods. Eventually, the "resizing" ctors will be phased out.
+ ///
+ MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
+
+ /// MachineInstr ctor - Work exactly the same as the ctor above, except that
+ /// the MachineInstr is created and added to the end of the specified basic
+ /// block.
+ ///
+ MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
+
+
+ /// replace - Support to rewrite a machine instruction in place: for now,
+ /// simply replace() and then set new operands with Set.*Operand methods
+ /// below.
+ ///
+ void replace(MachineOpCode Opcode, unsigned numOperands);
+
+ // The opcode.
+ //
+ const MachineOpCode getOpcode() const { return opCode; }
+ const MachineOpCode getOpCode() const { return opCode; }
//
// Information about explicit operands of the instruction
//
- unsigned int getNumOperands () const { return operands.size(); }
-
- bool operandIsDefined(unsigned i) const;
-
- const MachineOperand& getOperand (unsigned i) const;
- MachineOperand& getOperand (unsigned i);
+ unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
+ const MachineOperand& getOperand(unsigned i) const {
+ assert(i < getNumOperands() && "getOperand() out of range!");
+ return operands[i];
+ }
+ MachineOperand& getOperand(unsigned i) {
+ assert(i < getNumOperands() && "getOperand() out of range!");
+ return operands[i];
+ }
+
+ MachineOperand::MachineOperandType getOperandType(unsigned i) const {
+ return getOperand(i).getType();
+ }
+
+ bool operandIsDefined(unsigned i) const {
+ return getOperand(i).opIsDef();
+ }
+
+ bool operandIsDefinedAndUsed(unsigned i) const {
+ return getOperand(i).opIsDefAndUse();
+ }
+
//
// Information about implicit operands of the instruction
//
- unsigned getNumImplicitRefs() const{return implicitRefs.size();}
+ unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
- bool implicitRefIsDefined(unsigned i) const;
-
- const Value* getImplicitRef (unsigned i) const;
- Value* getImplicitRef (unsigned i);
+ const Value* getImplicitRef(unsigned i) const {
+ return getImplicitOp(i).getVRegValue();
+ }
+ Value* getImplicitRef(unsigned i) {
+ return getImplicitOp(i).getVRegValue();
+ }
+
+ bool implicitRefIsDefined(unsigned i) const {
+ return getImplicitOp(i).opIsDef();
+ }
+ bool implicitRefIsDefinedAndUsed(unsigned i) const {
+ return getImplicitOp(i).opIsDefAndUse();
+ }
+ inline void addImplicitRef (Value* V,
+ bool isDef=false,bool isDefAndUse=false);
+ inline void setImplicitRef (unsigned i, Value* V,
+ bool isDef=false, bool isDefAndUse=false);
+
+ //
+ // Information about registers used in this instruction
+ //
+ const std::vector<bool> &getRegsUsed() const { return regsUsed; }
+ // insertUsedReg - Add a register to the Used registers set...
+ void insertUsedReg(unsigned Reg) {
+ if (Reg >= regsUsed.size())
+ regsUsed.resize(Reg+1);
+ regsUsed[Reg] = true;
+ }
+
//
// Debugging support
- //
- void dump (unsigned int indent = 0) const;
+ //
+ void print(std::ostream &OS, const TargetMachine &TM) const;
+ void dump() const;
friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
-
//
// Define iterators to access the Value operands of the Machine Instruction.
+ // Note that these iterators only enumerate the explicit operands.
// begin() and end() are defined to produce these iterators...
//
template<class _MI, class _V> class ValOpIterator;
typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
-
// Access to set the operands when building the machine instruction
- void SetMachineOperandVal(unsigned i,
- MachineOperand::MachineOperandType operandType,
- Value* _val, bool isDef=false);
- void SetMachineOperandConst(unsigned i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue);
- void SetMachineOperandReg(unsigned i,
- int regNum,
- bool isDef=false,
- bool isCCReg=false);
-
- void addImplicitRef (Value* val,
- bool isDef=false);
+ //
+ void SetMachineOperandVal (unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ Value* V,
+ bool isDef=false,
+ bool isDefAndUse=false);
+
+ void SetMachineOperandConst (unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ int64_t intValue);
+
+ void SetMachineOperandReg (unsigned i,
+ int regNum,
+ bool isDef=false);
+
+ //===--------------------------------------------------------------------===//
+ // Accessors to add operands when building up machine instructions
+ //
+
+ /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
+ /// operands list...
+ ///
+ void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
+ !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
+ }
+
+ void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
+ UTy));
+ }
+
+ /// addRegOperand - Add a symbolic virtual register reference...
+ ///
+ void addRegOperand(int reg, bool isDef) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ isDef ? MOTy::Def : MOTy::Use));
+ }
+
+ /// addRegOperand - Add a symbolic virtual register reference...
+ ///
+ void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
+ UTy));
+ }
+
+ /// addPCDispOperand - Add a PC relative displacement operand to the MI
+ ///
+ void addPCDispOperand(Value *V) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
+ MOTy::Use));
+ }
+
+ /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
+ ///
+ void addMachineRegOperand(int reg, bool isDef) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
+ isDef ? MOTy::Def : MOTy::Use));
+ insertUsedReg(reg);
+ }
+
+ /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
+ ///
+ void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
+ UTy));
+ insertUsedReg(reg);
+ }
+
+ /// addZeroExtImmOperand - Add a zero extended constant argument to the
+ /// machine instruction.
+ ///
+ void addZeroExtImmOperand(int64_t intValue) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(intValue,
+ MachineOperand::MO_UnextendedImmed));
+ }
+
+ /// addSignExtImmOperand - Add a zero extended constant argument to the
+ /// machine instruction.
+ ///
+ void addSignExtImmOperand(int64_t intValue) {
+ assert(!OperandsComplete() &&
+ "Trying to add an operand to a machine instr that is already done!");
+ operands.push_back(MachineOperand(intValue,
+ MachineOperand::MO_SignExtendedImmed));
+ }
+
+
+ unsigned substituteValue(const Value* oldVal, Value* newVal,
+ bool defsOnly = true);
+
+ void setOperandHi32(unsigned i) { operands[i].markHi32(); }
+ void setOperandLo32(unsigned i) { operands[i].markLo32(); }
+ void setOperandHi64(unsigned i) { operands[i].markHi64(); }
+ void setOperandLo64(unsigned i) { operands[i].markLo64(); }
- void setImplicitRef (unsigned i,
- Value* val,
- bool isDef=false);
+
+ // SetRegForOperand - Replaces the Value for the operand with its allocated
+ // physical register after register allocation is complete.
+ //
+ void SetRegForOperand(unsigned i, int regNum);
+ //
+ // Iterator to enumerate machine operands.
+ //
template<class MITy, class VTy>
- class ValOpIterator : public std::forward_iterator<VTy, ptrdiff_t> {
+ class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
unsigned i;
MITy MI;
- inline void skipToNextVal() {
+ void skipToNextVal() {
while (i < MI->getNumOperands() &&
- !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
- MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
- && MI->getOperand(i).getVRegValue() != 0))
+ !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
+ MI->getOperandType(i) == MachineOperand::MO_CCRegister)
+ && MI->getOperand(i).getVRegValue() != 0))
++i;
}
public:
typedef ValOpIterator<MITy, VTy> _Self;
- inline VTy operator*() const { return MI->getOperand(i).getVRegValue(); }
-
- const MachineOperand &getMachineOperand() const {
- return MI->getOperand(i);
+ inline VTy operator*() const {
+ return MI->getOperand(i).getVRegValue();
}
+ const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
+ MachineOperand &getMachineOperand() { return MI->getOperand(i);}
+
inline VTy operator->() const { return operator*(); }
-
- inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
-
+
+ inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
+ inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
+
inline _Self& operator++() { i++; skipToNextVal(); return *this; }
inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
};
-inline MachineOperand&
-MachineInstr::getOperand(unsigned int i)
-{
- assert(i < operands.size() && "getOperand() out of range!");
- return operands[i];
-}
-
-inline const MachineOperand&
-MachineInstr::getOperand(unsigned int i) const
-{
- assert(i < operands.size() && "getOperand() out of range!");
- return operands[i];
-}
-
-inline bool
-MachineInstr::operandIsDefined(unsigned int i) const
-{
- return getOperand(i).opIsDef();
-}
-
-inline bool
-MachineInstr::implicitRefIsDefined(unsigned int i) const
-{
- assert(i < implicitIsDef.size() && "operand out of range!");
- return implicitIsDef[i];
-}
-
-inline const Value*
-MachineInstr::getImplicitRef(unsigned int i) const
-{
- assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
- return implicitRefs[i];
-}
-
-inline Value*
-MachineInstr::getImplicitRef(unsigned int i)
-{
- assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
- return implicitRefs[i];
-}
-
-inline void
-MachineInstr::addImplicitRef(Value* val,
- bool isDef)
+// Define here to enable inlining of the functions used.
+//
+void MachineInstr::addImplicitRef(Value* V,
+ bool isDef,
+ bool isDefAndUse)
{
- implicitRefs.push_back(val);
- implicitIsDef.push_back(isDef);
+ ++numImplicitRefs;
+ addRegOperand(V, isDef, isDefAndUse);
}
-inline void
-MachineInstr::setImplicitRef(unsigned int i,
- Value* val,
- bool isDef)
+void MachineInstr::setImplicitRef(unsigned i,
+ Value* V,
+ bool isDef,
+ bool isDefAndUse)
{
- assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
- implicitRefs[i] = val;
- implicitIsDef[i] = isDef;
+ assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
+ SetMachineOperandVal(i + getNumOperands(),
+ MachineOperand::MO_VirtualRegister,
+ V, isDef, isDefAndUse);
}
-
-//---------------------------------------------------------------------------
-// class MachineCodeForBasicBlock
-//
-// Purpose:
-// Representation of the sequence of machine instructions created
-// for a basic block.
-//---------------------------------------------------------------------------
-
-
-class MachineCodeForBasicBlock {
- std::vector<MachineInstr*> Insts;
-public:
- ~MachineCodeForBasicBlock() {
-#if 0
- for (unsigned i = 0, e = Insts.size(); i != e; ++i)
- delete Insts[i];
-#endif
- }
-
- typedef std::vector<MachineInstr*>::iterator iterator;
- typedef std::vector<MachineInstr*>::const_iterator const_iterator;
- typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
- typedef std::reverse_iterator<iterator> reverse_iterator;
-
- unsigned size() const { return Insts.size(); }
- bool empty() const { return Insts.empty(); }
-
- MachineInstr * operator[](unsigned i) const { return Insts[i]; }
- MachineInstr *&operator[](unsigned i) { return Insts[i]; }
-
- MachineInstr *front() const { return Insts.front(); }
- MachineInstr *back() const { return Insts.back(); }
-
- iterator begin() { return Insts.begin(); }
- const_iterator begin() const { return Insts.begin(); }
- iterator end() { return Insts.end(); }
- const_iterator end() const { return Insts.end(); }
- reverse_iterator rbegin() { return Insts.rbegin(); }
- const_reverse_iterator rbegin() const { return Insts.rbegin(); }
- reverse_iterator rend () { return Insts.rend(); }
- const_reverse_iterator rend () const { return Insts.rend(); }
-
- void push_back(MachineInstr *MI) { Insts.push_back(MI); }
- template<typename IT>
- void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); }
- iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M); }
-
- // erase - Remove the specified range from the instruction list. This does
- // not delete in instructions removed.
- //
- iterator erase(iterator I, iterator E) { return Insts.erase(I, E); }
-
- MachineInstr *pop_back() {
- MachineInstr *R = back();
- Insts.pop_back();
- return R;
- }
-};
-
-
//---------------------------------------------------------------------------
// Debugging Support
//---------------------------------------------------------------------------
+std::ostream& operator<< (std::ostream& os,
+ const MachineInstr& minstr);
-std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
-
-
-std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
+std::ostream& operator<< (std::ostream& os,
+ const MachineOperand& mop);
-
-void PrintMachineInstructions(const Function *F);
+void PrintMachineInstructions (const Function *F);
#endif
projects / oota-llvm.git / blobdiff