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[PATCH] kill SET_LINKS/REMOVE_LINKS
[firefly-linux-kernel-4.4.55.git] / include / asm-powerpc / cputable.h
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index f4d5089324673c5c1293d981edbf88e54c420818..fe45f6f3a4bee59fa4d4757834190ff4c5e44b96 100644 (file)
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -19,6 +19,9 @@
 #define PPC_FEATURE_POWER5             0x00040000
 #define PPC_FEATURE_POWER5_PLUS                0x00020000
 #define PPC_FEATURE_CELL               0x00010000
+#define PPC_FEATURE_BOOKE              0x00008000
+#define PPC_FEATURE_SMT                        0x00004000
+#define PPC_FEATURE_ICACHE_SNOOP       0x00002000
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
@@ -27,10 +30,17 @@
  * via the mkdefs mechanism.
  */
 struct cpu_spec;
-struct op_powerpc_model;
 
 typedef        void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
 
+enum powerpc_oprofile_type {
+       PPC_OPROFILE_INVALID = 0,
+       PPC_OPROFILE_RS64 = 1,
+       PPC_OPROFILE_POWER4 = 2,
+       PPC_OPROFILE_G4 = 3,
+       PPC_OPROFILE_BOOKE = 4,
+};
+
 struct cpu_spec {
        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
        unsigned int    pvr_mask;
@@ -56,7 +66,10 @@ struct cpu_spec {
        char            *oprofile_cpu_type;
 
        /* Processor specific oprofile operations */
-       struct op_powerpc_model *oprofile_model;
+       enum powerpc_oprofile_type oprofile_type;
+
+       /* Name of processor class, for the ELF AT_PLATFORM entry */
+       char            *platform;
 };
 
 extern struct cpu_spec         *cur_cpu_spec;
@@ -89,37 +102,40 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_NEED_COHERENT          ASM_CONST(0x0000000000020000)
 #define CPU_FTR_NO_BTIC                        ASM_CONST(0x0000000000040000)
 #define CPU_FTR_BIG_PHYS               ASM_CONST(0x0000000000080000)
-#define CPU_FTR_NODSISRALIGN           ASM_CONST(0x0000000000100000)
+#define CPU_FTR_NODSISRALIGN           ASM_CONST(0x0000000000100000)
 
 #ifdef __powerpc64__
 /* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB                    ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE               ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                         ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE              ASM_CONST(0x0000000800000000)
-#define CPU_FTR_IABR                   ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA                          ASM_CONST(0x0000004000000000)
+#define CPU_FTR_SLB                    ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE               ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL                 ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE              ASM_CONST(0x0000000800000000)
+#define CPU_FTR_IABR                   ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA                  ASM_CONST(0x0000004000000000)
 #define CPU_FTR_CTRL                   ASM_CONST(0x0000008000000000)
-#define CPU_FTR_SMT                    ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE        ASM_CONST(0x0000020000000000)
+#define CPU_FTR_SMT                    ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE                ASM_CONST(0x0000020000000000)
 #define CPU_FTR_LOCKLESS_TLBIE         ASM_CONST(0x0000040000000000)
 #define CPU_FTR_MMCRA_SIHV             ASM_CONST(0x0000080000000000)
 #define CPU_FTR_CI_LARGE_PAGE          ASM_CONST(0x0000100000000000)
+#define CPU_FTR_PAUSE_ZERO             ASM_CONST(0x0000200000000000)
+#define CPU_FTR_PURR                   ASM_CONST(0x0000400000000000)
 #else
 /* ensure on 32b processors the flags are available for compiling but
  * don't do anything */
-#define CPU_FTR_SLB                    ASM_CONST(0x0)
-#define CPU_FTR_16M_PAGE               ASM_CONST(0x0)
-#define CPU_FTR_TLBIEL                         ASM_CONST(0x0)
-#define CPU_FTR_NOEXECUTE              ASM_CONST(0x0)
-#define CPU_FTR_IABR                   ASM_CONST(0x0)
-#define CPU_FTR_MMCRA                          ASM_CONST(0x0)
+#define CPU_FTR_SLB                    ASM_CONST(0x0)
+#define CPU_FTR_16M_PAGE               ASM_CONST(0x0)
+#define CPU_FTR_TLBIEL                 ASM_CONST(0x0)
+#define CPU_FTR_NOEXECUTE              ASM_CONST(0x0)
+#define CPU_FTR_IABR                   ASM_CONST(0x0)
+#define CPU_FTR_MMCRA                  ASM_CONST(0x0)
 #define CPU_FTR_CTRL                   ASM_CONST(0x0)
-#define CPU_FTR_SMT                    ASM_CONST(0x0)
-#define CPU_FTR_COHERENT_ICACHE        ASM_CONST(0x0)
+#define CPU_FTR_SMT                    ASM_CONST(0x0)
+#define CPU_FTR_COHERENT_ICACHE                ASM_CONST(0x0)
 #define CPU_FTR_LOCKLESS_TLBIE         ASM_CONST(0x0)
 #define CPU_FTR_MMCRA_SIHV             ASM_CONST(0x0)
 #define CPU_FTR_CI_LARGE_PAGE          ASM_CONST(0x0)
+#define CPU_FTR_PURR                   ASM_CONST(0x0)
 #endif
 
 #ifndef __ASSEMBLY__
@@ -147,9 +163,11 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we
- * have a 74[45]x and an MPC107 host bridge.
+ * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
+ * it for PCI "streaming/prefetch" to work properly.
  */
-#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
+       || defined(CONFIG_PPC_83xx)
 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 #else
 #define CPU_FTR_COMMON                  0
@@ -265,7 +283,8 @@ enum {
        CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
        CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
-           CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+           CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS |
+           CPU_FTR_COMMON,
        CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
        CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
@@ -301,10 +320,11 @@ enum {
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
            CPU_FTR_MMCRA | CPU_FTR_SMT |
            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
-           CPU_FTR_MMCRA_SIHV,
+           CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR,
        CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
-           CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
+           CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
+           CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
        CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
 #endif
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