Make Observer.Stress test not fail under load

[folly.git] / folly / experimental / Instructions.h

diff --git a/folly/experimental/Instructions.h b/folly/experimental/Instructions.h
index 6a1d6ed653be3819c6664e6c4f6fbb3cc3310475..f8368942f0393dc955e10931f4a1fe100b66a181 100644 (file)
--- a/folly/experimental/Instructions.h
+++ b/folly/experimental/Instructions.h
@@ -17,9 +17,13 @@
 #pragma once
 
 #include <glog/logging.h>
+
+#ifdef _MSC_VER
 #include <immintrin.h>
+#endif
 
 #include <folly/CpuId.h>
+#include <folly/Portability.h>
 #include <folly/portability/Builtins.h>
 
 namespace folly { namespace compression { namespace instructions {
@@ -33,19 +37,21 @@ namespace folly { namespace compression { namespace instructions {
 // use explicitly.
 
 struct Default {
-  static bool supported(const folly::CpuId& /* cpuId */ = {}) { return true; }
-  static inline uint64_t popcount(uint64_t value) {
+  static bool supported(const folly::CpuId& /* cpuId */ = {}) {
+    return true;
+  }
+  static FOLLY_ALWAYS_INLINE uint64_t popcount(uint64_t value) {
     return __builtin_popcountll(value);
   }
-  static inline int ctz(uint64_t value) {
+  static FOLLY_ALWAYS_INLINE int ctz(uint64_t value) {
     DCHECK_GT(value, 0);
     return __builtin_ctzll(value);
   }
-  static inline int clz(uint64_t value) {
+  static FOLLY_ALWAYS_INLINE int clz(uint64_t value) {
     DCHECK_GT(value, 0);
     return __builtin_clzll(value);
   }
-  static inline uint64_t blsr(uint64_t value) {
+  static FOLLY_ALWAYS_INLINE uint64_t blsr(uint64_t value) {
     return value & (value - 1);
   }
 };
@@ -54,11 +60,11 @@ struct Nehalem : public Default {
   static bool supported(const folly::CpuId& cpuId = {}) {
     return cpuId.popcnt();
   }
-  static inline uint64_t popcount(uint64_t value)
-      FOLLY_TARGET_ATTRIBUTE("popcnt") {
+
+  static FOLLY_ALWAYS_INLINE uint64_t popcount(uint64_t value) {
     // POPCNT is supported starting with Intel Nehalem, AMD K10.
-#if defined(__GNUC__) && !__GNUC_PREREQ(4, 9)
-    // GCC 4.8 doesn't support the intrinsics.
+#if defined(__GNUC__) || defined(__clang__)
+    // GCC and Clang won't inline the intrinsics.
     uint64_t result;
     asm ("popcntq %1, %0" : "=r" (result) : "r" (value));
     return result;
@@ -72,11 +78,12 @@ struct Haswell : public Nehalem {
   static bool supported(const folly::CpuId& cpuId = {}) {
     return Nehalem::supported(cpuId) && cpuId.bmi1();
   }
-  static inline uint64_t blsr(uint64_t value) FOLLY_TARGET_ATTRIBUTE("bmi") {
+
+  static FOLLY_ALWAYS_INLINE uint64_t blsr(uint64_t value) {
     // BMI1 is supported starting with Intel Haswell, AMD Piledriver.
     // BLSR combines two instuctions into one and reduces register pressure.
-#if defined(__GNUC__) && !__GNUC_PREREQ(4, 9)
-    // GCC 4.8 doesn't support the intrinsics.
+#if defined(__GNUC__) || defined(__clang__)
+    // GCC and Clang won't inline the intrinsics.
     uint64_t result;
     asm ("blsrq %1, %0" : "=r" (result) : "r" (value));
     return result;
@@ -86,4 +93,4 @@ struct Haswell : public Nehalem {
   }
 };
 
-}}}  // namespaces
+}}} // namespaces