{
struct musb *musb = hci;
void __iomem *reg_base = musb->ctrl_base;
+ struct usb_otg *otg = musb->xceiv->otg;
unsigned long flags;
irqreturn_t ret = IRQ_NONE;
u32 status;
WARNING("VBUS error workaround (delay coming)\n");
} else if (is_host_enabled(musb) && drvvbus) {
MUSB_HST_MODE(musb);
- musb->xceiv->default_a = 1;
+ otg->default_a = 1;
musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
portstate(musb->port1_status |= USB_PORT_STAT_POWER);
del_timer(&otg_workaround);
} else {
musb->is_active = 0;
MUSB_DEV_MODE(musb);
- musb->xceiv->default_a = 0;
+ otg->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
goto fail;
usb_nop_xceiv_register();
- musb->xceiv = otg_get_transceiver();
+ musb->xceiv = usb_get_transceiver();
if (!musb->xceiv)
goto fail;
phy_off();
- otg_put_transceiver(musb->xceiv);
+ usb_put_transceiver(musb->xceiv);
usb_nop_xceiv_unregister();
return 0;