};
/* non-EHCI USB system interface registers (Big Endian) */
-#ifdef CONFIG_ARCH_TEGRA
-struct usb_sys_interface {
- u32 suspend_ctrl;
- u32 vbus_sensors;
- u32 vbus_wakeup;
- u32 vbus_alt_status;
- u32 legacy_ctrl;
-};
-#else
struct usb_sys_interface {
u32 snoop1;
u32 snoop2;
u8 res[236];
u32 control; /* General Purpose Control Register */
};
-#endif
/* ep0 transfer state */
#define WAIT_FOR_SETUP 0
/* Alignment requirements; must be a power of two */
#define DTD_ALIGNMENT 0x20
#define QH_ALIGNMENT 2048
-#define QH_OFFSET 0x1000
/* Controller dma boundary */
#define UDC_DMA_BOUNDARY 0x1000
-#define USB_SYS_VBUS_ASESSION_INT_EN 0x10000
-#define USB_SYS_VBUS_ASESSION_CHANGED 0x20000
-#define USB_SYS_VBUS_ASESSION 0x40000
-#define USB_SYS_VBUS_WAKEUP_ENABLE 0x40000000
-#define USB_SYS_VBUS_WAKEUP_INT_ENABLE 0x100
-#define USB_SYS_VBUS_WAKEUP_INT_STATUS 0x200
-#define USB_SYS_VBUS_STATUS 0x400
-
/*-------------------------------------------------------------------------*/
/* ### driver private data
#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
struct platform_device;
-#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_TEGRA)
+#ifdef CONFIG_ARCH_MXC
int fsl_udc_clk_init(struct platform_device *pdev);
void fsl_udc_clk_finalize(struct platform_device *pdev);
void fsl_udc_clk_release(void);
-void fsl_udc_clk_suspend(void);
-void fsl_udc_clk_resume(void);
#else
static inline int fsl_udc_clk_init(struct platform_device *pdev)
{
static inline void fsl_udc_clk_release(void)
{
}
-static inline void fsl_udc_clk_suspend(void)
-{
-}
-static inline void fsl_udc_clk_resume(void)
-{
-}
#endif
#endif