#include "fsl_usb2_udc.h"
-#ifdef CONFIG_ARCH_TEGRA
-#define DRIVER_DESC "NVidia Tegra High-Speed USB SOC Device Controller driver"
-#else
#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
-#endif
#define DRIVER_AUTHOR "Li Yang/Jiang Bo"
#define DRIVER_VERSION "Apr 20, 2007"
#define DMA_ADDR_INVALID (~(dma_addr_t)0)
-#define STATUS_BUFFER_SIZE 8
-#ifdef CONFIG_ARCH_TEGRA
-static const char driver_name[] = "fsl-tegra-udc";
-#else
static const char driver_name[] = "fsl-usb2-udc";
-#endif
static const char driver_desc[] = DRIVER_DESC;
static struct usb_dr_device *dr_regs;
};
static void fsl_ep_fifo_flush(struct usb_ep *_ep);
-static int reset_queues(struct fsl_udc *udc);
#ifdef CONFIG_PPC32
#define fsl_readl(addr) in_le32(addr)
#define fsl_writel(val32, addr) writel(val32, addr)
#endif
-/*
- * High speed test mode packet(53 bytes).
- * See USB 2.0 spec, section 7.1.20.
- */
-static const u8 fsl_udc_test_packet[53] = {
- /* JKJKJKJK x9 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* JJKKJJKK x8 */
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- /* JJJJKKKK x8 */
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
- /* JJJJJJJKKKKKKK x8 */
- 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- /* JJJJJJJK x8 */
- 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
- /* JKKKKKKK x10, JK */
- 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
-};
-
/********************************************************************
* Internal Used Function
********************************************************************/
Internal Hardware related function
------------------------------------------------------------------*/
-#define FSL_UDC_RESET_TIMEOUT 1000
-static int dr_controller_reset(struct fsl_udc *udc)
-{
- unsigned int tmp;
- unsigned long timeout;
-
- /* Stop and reset the usb controller */
- tmp = fsl_readl(&dr_regs->usbcmd);
- tmp &= ~USB_CMD_RUN_STOP;
- fsl_writel(tmp, &dr_regs->usbcmd);
-
- tmp = fsl_readl(&dr_regs->usbcmd);
- tmp |= USB_CMD_CTRL_RESET;
- fsl_writel(tmp, &dr_regs->usbcmd);
-
- /* Wait for reset to complete */
- timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
- while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
- if (time_after(jiffies, timeout)) {
- ERR("udc reset timeout!\n");
- return -ETIMEDOUT;
- }
- cpu_relax();
- }
- return 0;
-}
-
static int dr_controller_setup(struct fsl_udc *udc)
{
unsigned int tmp, portctrl;
-#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
+#ifndef CONFIG_ARCH_MXC
unsigned int ctrl;
#endif
-#ifdef CONFIG_ARCH_TEGRA
unsigned long timeout;
-#endif
- int status;
+#define FSL_UDC_RESET_TIMEOUT 1000
/* Config PHY interface */
portctrl = fsl_readl(&dr_regs->portsc1);
}
fsl_writel(portctrl, &dr_regs->portsc1);
- status = dr_controller_reset(udc);
- if (status)
- return status;
+ /* Stop and reset the usb controller */
+ tmp = fsl_readl(&dr_regs->usbcmd);
+ tmp &= ~USB_CMD_RUN_STOP;
+ fsl_writel(tmp, &dr_regs->usbcmd);
- /* Set the controller as device mode */
- tmp = fsl_readl(&dr_regs->usbmode);
- tmp |= USB_MODE_CTRL_MODE_DEVICE;
- /* Disable Setup Lockout */
- tmp |= USB_MODE_SETUP_LOCK_OFF;
- fsl_writel(tmp, &dr_regs->usbmode);
+ tmp = fsl_readl(&dr_regs->usbcmd);
+ tmp |= USB_CMD_CTRL_RESET;
+ fsl_writel(tmp, &dr_regs->usbcmd);
-#ifdef CONFIG_ARCH_TEGRA
- /* Wait for controller to switch to device mode */
+ /* Wait for reset to complete */
timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
- while ((fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_DEVICE) !=
- USB_MODE_CTRL_MODE_DEVICE) {
+ while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
if (time_after(jiffies, timeout)) {
- ERR("udc device mode setup timeout!\n");
+ ERR("udc reset timeout!\n");
return -ETIMEDOUT;
}
cpu_relax();
}
-#endif
+
+ /* Set the controller as device mode */
+ tmp = fsl_readl(&dr_regs->usbmode);
+ tmp |= USB_MODE_CTRL_MODE_DEVICE;
+ /* Disable Setup Lockout */
+ tmp |= USB_MODE_SETUP_LOCK_OFF;
+ fsl_writel(tmp, &dr_regs->usbmode);
/* Clear the setup status */
fsl_writel(0, &dr_regs->usbsts);
fsl_readl(&dr_regs->endpointlistaddr));
/* Config control enable i/o output, cpu endian register */
-#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
+#ifndef CONFIG_ARCH_MXC
ctrl = __raw_readl(&usb_sys_regs->control);
ctrl |= USB_CTRL_IOENB;
__raw_writel(ctrl, &usb_sys_regs->control);
static void dr_controller_run(struct fsl_udc *udc)
{
u32 temp;
-#ifdef CONFIG_ARCH_TEGRA
- unsigned long timeout;
-#define FSL_UDC_RUN_TIMEOUT 1000
-#endif
- /* Clear stopped bit */
- udc->stopped = 0;
/* Enable DR irq reg */
temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
fsl_writel(temp, &dr_regs->usbintr);
+ /* Clear stopped bit */
+ udc->stopped = 0;
+
/* Set the controller as device mode */
temp = fsl_readl(&dr_regs->usbmode);
temp |= USB_MODE_CTRL_MODE_DEVICE;
temp |= USB_CMD_RUN_STOP;
fsl_writel(temp, &dr_regs->usbcmd);
-#ifdef CONFIG_ARCH_TEGRA
- /* Wait for controller to start */
- timeout = jiffies + FSL_UDC_RUN_TIMEOUT;
- while ((fsl_readl(&dr_regs->usbcmd) & USB_CMD_RUN_STOP) !=
- USB_CMD_RUN_STOP) {
- if (time_after(jiffies, timeout)) {
- ERR("udc start timeout!\n");
- return;
- }
- cpu_relax();
- }
-#endif
-
return;
}
? (1 << (ep_index(ep) + 16))
: (1 << (ep_index(ep)));
- /* Flush all the dTD structs out to memory */
- wmb();
-
/* check if the pipe is empty */
if (!(list_empty(&ep->queue))) {
/* Add td to the end */
lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
lastreq->tail->next_td_ptr =
cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
- wmb();
/* Read prime bit, if 1 goto done */
if (fsl_readl(&dr_regs->endpointprime) & bitmask)
goto out;
* @is_last: return flag if it is the last dTD of the request
* return: pointer to the built dTD */
static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
- dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
+ dma_addr_t *dma, int *is_last)
{
u32 swap_temp;
struct ep_td_struct *dtd;
*length = min(req->req.length - req->req.actual,
(unsigned)EP_MAX_LENGTH_TRANSFER);
- dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
+ dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
if (dtd == NULL)
return dtd;
}
/* Generate dtd chain for a request */
-static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
+static int fsl_req_to_dtd(struct fsl_req *req)
{
unsigned count;
int is_last;
dma_addr_t dma;
do {
- dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
+ dtd = fsl_build_dtd(req, &count, &dma, &is_last);
if (dtd == NULL)
return -ENOMEM;
{
struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
struct fsl_req *req = container_of(_req, struct fsl_req, req);
- struct fsl_udc *udc = ep->udc;
+ struct fsl_udc *udc;
unsigned long flags;
- enum dma_data_direction dir;
int is_iso = 0;
- int status;
/* catch various bogus parameters */
if (!_req || !req->req.complete || !req->req.buf
VDBG("%s, bad params", __func__);
return -EINVAL;
}
-
- spin_lock_irqsave(&udc->lock, flags);
-
- if (unlikely(!ep->desc)) {
+ if (unlikely(!_ep || !ep->desc)) {
VDBG("%s, bad ep", __func__);
- spin_unlock_irqrestore(&udc->lock, flags);
return -EINVAL;
}
-
if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
- if (req->req.length > ep->ep.maxpacket) {
- spin_unlock_irqrestore(&udc->lock, flags);
+ if (req->req.length > ep->ep.maxpacket)
return -EMSGSIZE;
- }
is_iso = 1;
}
- dir = ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
-
- spin_unlock_irqrestore(&udc->lock, flags);
-
+ udc = ep->udc;
if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
return -ESHUTDOWN;
/* map virtual address to hardware */
if (req->req.dma == DMA_ADDR_INVALID) {
- req->req.dma = dma_map_single(udc->gadget.dev.parent,
- req->req.buf, req->req.length, dir);
+ req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
+ req->req.buf,
+ req->req.length, ep_is_in(ep)
+ ? DMA_TO_DEVICE
+ : DMA_FROM_DEVICE);
req->mapped = 1;
} else {
- dma_sync_single_for_device(udc->gadget.dev.parent,
- req->req.dma, req->req.length, dir);
+ dma_sync_single_for_device(ep->udc->gadget.dev.parent,
+ req->req.dma, req->req.length,
+ ep_is_in(ep)
+ ? DMA_TO_DEVICE
+ : DMA_FROM_DEVICE);
req->mapped = 0;
}
req->req.actual = 0;
req->dtd_count = 0;
-
- /* build dtds and push them to device queue */
- status = fsl_req_to_dtd(req, gfp_flags);
- if (status)
- goto err_unmap;
-
spin_lock_irqsave(&udc->lock, flags);
- /* re-check if the ep has not been disabled */
- if (unlikely(!ep->desc)) {
+ /* build dtds and push them to device queue */
+ if (!fsl_req_to_dtd(req)) {
+ fsl_queue_td(ep, req);
+ } else {
spin_unlock_irqrestore(&udc->lock, flags);
- status = -EINVAL;
- goto err_unmap;
+ return -ENOMEM;
}
- fsl_queue_td(ep, req);
-
/* Update ep0 state */
if ((ep_index(ep) == 0))
udc->ep0_state = DATA_STATE_XMIT;
spin_unlock_irqrestore(&udc->lock, flags);
return 0;
-
-err_unmap:
- if (req->mapped) {
- dma_unmap_single(udc->gadget.dev.parent,
- req->req.dma, req->req.length, dir);
- req->req.dma = DMA_ADDR_INVALID;
- req->mapped = 0;
- }
- return status;
}
/* dequeues (cancels, unlinks) an I/O request from an endpoint */
udc = container_of(gadget, struct fsl_udc, gadget);
spin_lock_irqsave(&udc->lock, flags);
-
VDBG("VBUS %s", is_active ? "on" : "off");
-
- if (udc->transceiver) {
- if (udc->vbus_active && !is_active) {
- /* reset all internal Queues and inform client driver */
- reset_queues(udc);
- /* stop the controller and turn off the clocks */
- dr_controller_stop(udc);
- dr_controller_reset(udc);
- spin_unlock_irqrestore(&udc->lock, flags);
- fsl_udc_clk_suspend();
- udc->vbus_active = 0;
- udc->usb_state = USB_STATE_DEFAULT;
- } else if (!udc->vbus_active && is_active) {
- spin_unlock_irqrestore(&udc->lock, flags);
- fsl_udc_clk_resume();
- /* setup the controller in the device mode */
- dr_controller_setup(udc);
- /* setup EP0 for setup packet */
- ep0_setup(udc);
- /* initialize the USB and EP states */
- udc->usb_state = USB_STATE_ATTACHED;
- udc->ep0_state = WAIT_FOR_SETUP;
- udc->ep0_dir = 0;
- udc->vbus_active = 1;
- /* start the controller */
- dr_controller_run(udc);
- }
- return 0;
- }
-
udc->vbus_active = (is_active != 0);
if (can_pullup(udc))
fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
req->req.complete = NULL;
req->dtd_count = 0;
- if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
+ if (fsl_req_to_dtd(req) == 0)
fsl_queue_td(ep, req);
else
return -ENOMEM;
req->dtd_count = 0;
/* prime the data phase */
- if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
+ if ((fsl_req_to_dtd(req) == 0))
fsl_queue_td(ep, req);
else /* no mem */
goto stall;
ep0stall(udc);
}
-static void udc_test_mode(struct fsl_udc *udc, u32 test_mode)
-{
- struct fsl_req *req;
- struct fsl_ep *ep;
- u32 portsc, bitmask;
- unsigned long timeout;
-
- /* Ack the ep0 IN */
- if (ep0_prime_status(udc, EP_DIR_IN))
- ep0stall(udc);
-
- /* get the ep0 */
- ep = &udc->eps[0];
- bitmask = ep_is_in(ep)
- ? (1 << (ep_index(ep) + 16))
- : (1 << (ep_index(ep)));
-
- timeout = jiffies + HZ;
- /* Wait until ep0 IN endpoint txfr is complete */
- while (!(fsl_readl(&dr_regs->endptcomplete) & bitmask)) {
- if (time_after(jiffies, timeout)) {
- pr_err("Timeout for Ep0 IN Ack\n");
- break;
- }
- cpu_relax();
- }
-
- switch (test_mode << PORTSCX_PTC_BIT_POS) {
- case PORTSCX_PTC_JSTATE:
- VDBG("TEST_J\n");
- break;
- case PORTSCX_PTC_KSTATE:
- VDBG("TEST_K\n");
- break;
- case PORTSCX_PTC_SEQNAK:
- VDBG("TEST_SE0_NAK\n");
- break;
- case PORTSCX_PTC_PACKET:
- VDBG("TEST_PACKET\n");
-
- /* get the ep and configure for IN direction */
- ep = &udc->eps[0];
- udc->ep0_dir = USB_DIR_IN;
-
- /* Initialize ep0 status request structure */
- req = container_of(fsl_alloc_request(NULL, GFP_ATOMIC),
- struct fsl_req, req);
- /* allocate a small amount of memory to get valid address */
- req->req.buf = kmalloc(sizeof(fsl_udc_test_packet), GFP_ATOMIC);
- req->req.dma = virt_to_phys(req->req.buf);
-
- /* Fill in the reqest structure */
- memcpy(req->req.buf, fsl_udc_test_packet, sizeof(fsl_udc_test_packet));
- req->ep = ep;
- req->req.length = sizeof(fsl_udc_test_packet);
- req->req.status = -EINPROGRESS;
- req->req.actual = 0;
- req->req.complete = NULL;
- req->dtd_count = 0;
- req->mapped = 0;
-
- dma_sync_single_for_device(ep->udc->gadget.dev.parent,
- req->req.dma, req->req.length,
- ep_is_in(ep)
- ? DMA_TO_DEVICE
- : DMA_FROM_DEVICE);
-
- /* prime the data phase */
- if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
- fsl_queue_td(ep, req);
- else /* no mem */
- goto stall;
-
- list_add_tail(&req->queue, &ep->queue);
- udc->ep0_state = DATA_STATE_XMIT;
- break;
- case PORTSCX_PTC_FORCE_EN:
- VDBG("TEST_FORCE_EN\n");
- break;
- default:
- ERR("udc unknown test mode[%d]!\n", test_mode);
- goto stall;
- }
-
- /* read the portsc register */
- portsc = fsl_readl(&dr_regs->portsc1);
- /* set the test mode selector */
- portsc |= test_mode << PORTSCX_PTC_BIT_POS;
- fsl_writel(portsc, &dr_regs->portsc1);
-
- /*
- * The device must have its power cycled to exit test mode.
- * See USB 2.0 spec, section 9.4.9 for test modes operation in "Set Feature"
- * See USB 2.0 spec, section 7.1.20 for test modes.
- */
- pr_info("udc entering the test mode, power cycle to exit test mode\n");
- return;
-stall:
- ep0stall(udc);
-}
-
static void setup_received_irq(struct fsl_udc *udc,
struct usb_ctrlrequest *setup)
{
{
int rc = -EOPNOTSUPP;
- if (setup->bRequestType == USB_RECIP_DEVICE &&
- wValue == USB_DEVICE_TEST_MODE) {
- /*
- * If the feature selector is TEST_MODE, then the most
- * significant byte of wIndex is used to specify the specific
- * test mode and the lower byte of wIndex must be zero.
- */
- udc_test_mode(udc, wIndex >> 8);
- return;
-
- } else if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
+ if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
== (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
int pipe = get_pipe_by_windex(wIndex);
struct fsl_ep *ep;
if (!bit_pos)
return;
-#ifdef CONFIG_ARCH_TEGRA
- /* XXX what's going on here */
- for (i = 0; i < udc->max_ep; i++) {
-#else
for (i = 0; i < udc->max_ep * 2; i++) {
-#endif
ep_num = i >> 1;
direction = i % 2;
/* Write 1s to the flush register */
fsl_writel(0xffffffff, &dr_regs->endptflush);
-#if defined(CONFIG_ARCH_TEGRA)
- /* When the bus reset is seen on Tegra, the PORTSCX_PORT_RESET bit
- * is not set */
- VDBG("Bus reset");
- /* Reset all the queues, include XD, dTD, EP queue
- * head and TR Queue */
- reset_queues(udc);
- udc->usb_state = USB_STATE_DEFAULT;
-#else
if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
VDBG("Bus reset");
/* Reset all the queues, include XD, dTD, EP queue
dr_controller_run(udc);
udc->usb_state = USB_STATE_ATTACHED;
}
-#endif
}
/*
irqreturn_t status = IRQ_NONE;
unsigned long flags;
- spin_lock_irqsave(&udc->lock, flags);
-
/* Disable ISR for OTG host mode */
- if (udc->stopped) {
- spin_unlock_irqrestore(&udc->lock, flags);
+ if (udc->stopped)
return IRQ_NONE;
- }
-
+ spin_lock_irqsave(&udc->lock, flags);
irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
/* Clear notification bits */
fsl_writel(irq_src, &dr_regs->usbsts);
}
/* Enable DR IRQ reg and Set usbcmd reg Run bit */
- if (!udc_controller->transceiver) {
- dr_controller_run(udc_controller);
- udc_controller->usb_state = USB_STATE_ATTACHED;
- udc_controller->ep0_state = WAIT_FOR_SETUP;
- udc_controller->ep0_dir = 0;
- }
-
+ dr_controller_run(udc_controller);
+ udc_controller->usb_state = USB_STATE_ATTACHED;
+ udc_controller->ep0_state = WAIT_FOR_SETUP;
+ udc_controller->ep0_dir = 0;
printk(KERN_INFO "%s: bind to driver %s\n",
udc_controller->gadget.name, driver->driver.name);
if (!driver || driver != udc_controller->driver || !driver->unbind)
return -EINVAL;
+ if (udc_controller->transceiver)
+ otg_set_peripheral(udc_controller->transceiver, NULL);
+
/* stop DR, disable intr */
dr_controller_stop(udc_controller);
#include <linux/seq_file.h>
-#ifdef CONFIG_ARCH_TEGRA
-static const char proc_filename[] = "driver/fsl_tegra_udc";
-#else
static const char proc_filename[] = "driver/fsl_usb2_udc";
-#endif
static int fsl_proc_read(char *page, char **start, off_t off, int count,
int *eof, void *_dev)
size -= t;
next += t;
-#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
+#ifndef CONFIG_ARCH_MXC
tmp_reg = usb_sys_regs->snoop1;
t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
size -= t;
static void fsl_udc_release(struct device *dev)
{
complete(udc_controller->done);
-#ifndef CONFIG_ARCH_TEGRA
dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
udc_controller->ep_qh, udc_controller->ep_qh_dma);
-#endif
kfree(udc_controller);
}
return -1;
}
-#ifdef CONFIG_ARCH_TEGRA
- /* Tegra uses hardware queue heads */
- size = udc->max_ep * sizeof(struct ep_queue_head);
- udc->ep_qh = (struct ep_queue_head *)((u8 *)dr_regs + QH_OFFSET);
- udc->ep_qh_dma = platform_get_resource(pdev, IORESOURCE_MEM, 0)->start +
- QH_OFFSET;
-#else
/* initialized QHs, take care of alignment */
size = udc->max_ep * sizeof(struct ep_queue_head);
if (size < QH_ALIGNMENT)
kfree(udc->eps);
return -1;
}
-#endif
udc->ep_qh_size = size;
udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
struct fsl_req, req);
/* allocate a small amount of memory to get valid address */
- udc->status_req->req.buf = dma_alloc_coherent(&pdev->dev,
- STATUS_BUFFER_SIZE, &udc->status_req->req.dma,
- GFP_KERNEL);
- if (!udc->status_req->req.buf) {
- ERR("alloc status_req buffer failed\n");
-#ifndef CONFIG_ARCH_TEGRA
- dma_free_coherent(&pdev->dev, size, udc->ep_qh, udc->ep_qh_dma);
-#endif
- kfree(udc->eps);
- return -ENOMEM;
- }
+ udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
+ udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
udc->resume_state = USB_STATE_NOTATTACHED;
udc->usb_state = USB_STATE_POWERED;
int ret = -ENODEV;
unsigned int i;
u32 dccparams;
-#if defined(CONFIG_ARCH_TEGRA)
- struct resource *res_sys = NULL;
-#endif
if (strcmp(pdev->name, driver_name)) {
VDBG("Wrong device");
goto err_release_mem_region;
}
-#if defined(CONFIG_ARCH_TEGRA)
- /* If the PHY registers are NOT provided as a seperate aperture, then
- * we should be using the registers inside the controller aperture. */
- res_sys = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (res_sys) {
- usb_sys_regs = ioremap(res_sys->start, resource_size(res_sys));
- if (!usb_sys_regs)
- goto err_release_mem_region;
- } else {
- usb_sys_regs = (struct usb_sys_interface *)
- ((u32)dr_regs + USB_DR_SYS_OFFSET);
- }
-#endif
-
-#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
+#ifndef CONFIG_ARCH_MXC
usb_sys_regs = (struct usb_sys_interface *)
((u32)dr_regs + USB_DR_SYS_OFFSET);
#endif
goto err_unregister;
}
create_proc_file();
-
-#ifdef CONFIG_USB_OTG_UTILS
- udc_controller->transceiver = otg_get_transceiver();
- if (udc_controller->transceiver) {
- dr_controller_stop(udc_controller);
- dr_controller_reset(udc_controller);
- fsl_udc_clk_suspend();
- udc_controller->vbus_active = 0;
- udc_controller->usb_state = USB_STATE_DEFAULT;
- otg_set_peripheral(udc_controller->transceiver, &udc_controller->gadget);
- }
-#else
-#ifdef CONFIG_ARCH_TEGRA
- /* Power down the phy if cable is not connected */
- if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS))
- fsl_udc_clk_suspend();
-#endif
-#endif
-
return 0;
err_unregister:
return -ENODEV;
udc_controller->done = &done;
- if (udc_controller->transceiver)
- otg_set_peripheral(udc_controller->transceiver, NULL);
-
fsl_udc_clk_release();
/* DR has been stopped in usb_gadget_unregister_driver() */
remove_proc_file();
/* Free allocated memory */
- dma_free_coherent(&pdev->dev, STATUS_BUFFER_SIZE,
- udc_controller->status_req->req.buf,
- udc_controller->status_req->req.dma);
+ kfree(udc_controller->status_req->req.buf);
kfree(udc_controller->status_req);
kfree(udc_controller->eps);
-----------------------------------------------------------------*/
static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
{
- if (udc_controller->transceiver &&
- udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL)
- return 0;
-
dr_controller_stop(udc_controller);
return 0;
}
*-----------------------------------------------------------------*/
static int fsl_udc_resume(struct platform_device *pdev)
{
- if (udc_controller->transceiver &&
- udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL)
- return 0;
-
/* Enable DR irq reg and set controller Run */
if (udc_controller->stopped) {
dr_controller_setup(udc_controller);
projects / firefly-linux-kernel-4.4.55.git / blobdiff