}
static const struct of_device_id usb20_host_of_match[] = {
+#ifdef CONFIG_ARM
{
.compatible = "rockchip,rk3188_usb20_host",
.data = &usb20host_pdata_rk3188,
.compatible = "rockchip,rk3126_usb20_host",
.data = &usb20host_pdata_rk3126,
},
+#endif
{},
};
dwc_otg_core_if_t *core_if = otg_dev->core_if;
struct dwc_otg_platform_data *pldata = otg_dev->pldata;
dctl_data_t dctl = {.d32 = 0 };
+ dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
dwc_otg_is_host_mode(core_if) ? "host" : "device");
- if (pldata->dwc_otg_uart_mode != NULL)
- pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
- if (pldata->phy_suspend != NULL)
- pldata->phy_suspend(pldata, USB_PHY_ENABLED);
if (dwc_otg_is_host_mode(core_if)) {
if (core_if->hcd_cb && core_if->hcd_cb->stop)
core_if->hcd_cb->stop(core_if->hcd_cb_p);
} else {
+ cancel_delayed_work_sync(&pcd->check_vbus_work);
/* soft disconnect */
dctl.d32 =
DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
/* Clear any pending interrupts */
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+ if (pldata->dwc_otg_uart_mode != NULL)
+ pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
+ if (pldata->phy_suspend != NULL)
+ pldata->phy_suspend(pldata, USB_PHY_ENABLED);
+
}
/**
}
static const struct of_device_id usb20_otg_of_match[] = {
+#ifdef CONFIG_ARM
{
.compatible = "rockchip,rk3188_usb20_otg",
.data = &usb20otg_pdata_rk3188,
.compatible = "rockchip,rk3126_usb20_otg",
.data = &usb20otg_pdata_rk3126,
},
+#endif
+#ifdef CONFIG_ARM64
{
.compatible = "rockchip,rk3368_usb20_otg",
.data = &usb20otg_pdata_rk3368,
},
+#endif
{ },
};
* perform initial actions required for Internal ADP logic.
*/
if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
- if (pldata->phy_status == USB_PHY_ENABLED) {
+ if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
+ pldata->phy_status == USB_PHY_ENABLED) {
pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
udelay(3);
pldata->clock_enable(pldata, 0);