*
* The Core Interface Layer has the following requirements:
* - Provides basic controller operations.
- * - Minimal use of OS services.
+ * - Minimal use of OS services.
* - The OS services used will be abstracted by using inline functions
* or macros.
*
#include "usbdev_rk.h"
#include "dwc_otg_hcd.h"
-static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
+static int dwc_otg_setup_params(dwc_otg_core_if_t *core_if);
/**
* This function is called to initialize the DWC_otg CSR data
* @param reg_base_addr Base address of DWC_otg core registers
*
*/
-dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr)
{
dwc_otg_core_if_t *core_if = 0;
dwc_otg_dev_if_t *dev_if = 0;
i, &dev_if->out_ep_regs[i]->doepctl);
}
- dev_if->speed = 0; // unknown
+ dev_if->speed = 0; /* unknown */
core_if->dev_if = dev_if;
core_if->hwcfg4.d32 =
DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
+ /* do not get HPTXFSIZ here, it's unused.
+ * set global_regs->hptxfsiz in dwc_otg_core_host_init.
+ * for 3.10a version, host20 FIFO can't be configed,
+ * because host20 hwcfg2.b.dynamic_fifo = 0.
+ */
+#if 0
/* Force host mode to get HPTXFSIZ exact power on value */
{
gusbcfg_data_t gusbcfg = {.d32 = 0 };
- gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+ gusbcfg.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
gusbcfg.b.force_host_mode = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
+ gusbcfg.d32);
dwc_mdelay(100);
core_if->hptxfsiz.d32 =
DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
- gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+ gusbcfg.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
gusbcfg.b.force_host_mode = 0;
- DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
+ gusbcfg.d32);
dwc_mdelay(100);
}
+#endif
DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
}
core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
- DWC_PRINTF("%p\n",&core_if->core_global_regs->gsnpsid);
+ DWC_PRINTF("%p\n", &core_if->core_global_regs->gsnpsid);
DWC_PRINTF("Core Release: %x.%x%x%x\n",
(core_if->snpsid >> 12 & 0xF),
(core_if->snpsid >> 8 & 0xF),
(core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
- core_if->wkp_tasklet = DWC_TASK_ALLOC("wkp_tasklet", w_wakeup_detected, core_if);
+ core_if->wkp_tasklet =
+ DWC_TASK_ALLOC("wkp_tasklet", w_wakeup_detected, core_if);
- if (dwc_otg_setup_params(core_if)) {
+ if (dwc_otg_setup_params(core_if))
DWC_WARN("Error while setting core params\n");
- }
core_if->hibernation_suspend = 0;
if (core_if->otg_ver)
/** ADP initialization */
dwc_otg_adp_init(core_if);
-
+
return core_if;
}
* This function frees the structures allocated by dwc_otg_cil_init().
*
* @param core_if The core interface pointer returned from
- * dwc_otg_cil_init().
+ * dwc_otg_cil_init().
*
*/
-void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
+void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
{
dctl_data_t dctl = {.d32 = 0 };
/* Disable all interrupts */
DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
DWC_WORKQ_FREE(core_if->wq_otg);
}
- if (core_if->dev_if) {
+ if (core_if->dev_if)
DWC_FREE(core_if->dev_if);
- }
- if (core_if->host_if) {
+ if (core_if->host_if)
DWC_FREE(core_if->host_if);
- }
/** Remove ADP Stuff */
dwc_otg_adp_remove(core_if);
- if (core_if->core_params) {
+ if (core_if->core_params)
DWC_FREE(core_if->core_params);
- }
- if (core_if->wkp_tasklet){
- DWC_TASK_FREE(core_if->wkp_tasklet);
- }
- if (core_if->srp_timer) {
+ if (core_if->wkp_tasklet)
+ DWC_TASK_FREE(core_if->wkp_tasklet);
+ if (core_if->srp_timer)
DWC_TIMER_FREE(core_if->srp_timer);
- }
+
DWC_FREE(core_if);
}
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
{
gahbcfg_data_t ahbcfg = {.d32 = 0 };
ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
{
gahbcfg_data_t ahbcfg = {.d32 = 0 };
ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
* @param core_if Programming view of the DWC_otg controller
*
*/
-static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
gintmsk_data_t intr_mask = {.d32 = 0 };
intr_mask.b.wkupintr = 1;
intr_mask.b.disconnect = 0;
intr_mask.b.usbsuspend = 1;
- //intr_mask.b.sessreqintr = 1;
+ /* intr_mask.b.sessreqintr = 1; */
#ifdef CONFIG_USB_DWC_OTG_LPM
- if (core_if->core_params->lpm_enable) {
+ if (core_if->core_params->lpm_enable)
intr_mask.b.lpmtranrcvd = 1;
- }
#endif
DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
}
* @param rem_wakeup - indicates whether resume is initiated by Device or Host.
* @param reset - indicates whether resume is initiated by Reset.
*/
-int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
+int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t *core_if,
int rem_wakeup, int reset)
{
gpwrdn_data_t gpwrdn = {.d32 = 0 };
return 1;
}
- DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
+ DWC_DEBUGPL(DBG_PCD, "%s called\n", __func__);
/* Switch-on voltage to the core */
gpwrdn.b.pwrdnswtch = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
gpwrdn.b.pwrdnclmp = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
- if (rem_wakeup) {
+ if (rem_wakeup)
dwc_udelay(70);
- }
/* Deassert Reset core */
gpwrdn.d32 = 0;
if (core_if->hibernation_suspend == 0) {
/*
- * Wait For Restore_done Interrupt. This mechanism of polling the
+ * Wait For Restore_done Interrupt. This mechanism of polling the
* interrupt is introduced to avoid any possible race conditions
*/
do {
if (gintsts.b.restoredone) {
gintsts.d32 = 0;
gintsts.b.restoredone = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->
- gintsts, gintsts.d32);
+ DWC_WRITE_REG32(&core_if->
+ core_global_regs->gintsts,
+ gintsts.d32);
DWC_PRINTF("Restore Done Interrupt seen\n");
break;
}
dwc_udelay(10);
} while (--timeout);
if (!timeout) {
- DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
+ DWC_PRINTF
+ ("Restore Done interrupt wasn't generated here\n");
}
}
/* Clear all pending interupts */
if (!rem_wakeup) {
/* Set Device programming done bit */
dctl.b.pwronprgdone = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
+ dctl.d32);
} else {
/* Start Remote Wakeup Signaling */
dctl.d32 = core_if->dr_backup->dctl;
dctl.b.rmtwkupsig = 1;
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
+ dctl.d32);
}
dwc_mdelay(2);
dwc_mdelay(7);
dctl.d32 = 0;
dctl.b.rmtwkupsig = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
+ dctl.d32, 0);
}
core_if->hibernation_suspend = 0;
* @param rem_wakeup - indicates whether resume is initiated by Device or Host.
* @param reset - indicates whether resume is initiated by Reset.
*/
-int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
+int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t *core_if,
int rem_wakeup, int reset)
{
gpwrdn_data_t gpwrdn = {.d32 = 0 };
int timeout = 2000;
- DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
+ DWC_DEBUGPL(DBG_HCD, "%s called\n", __func__);
/* Switch-on voltage to the core */
gpwrdn.b.pwrdnswtch = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
gpwrdn.b.pwrdnclmp = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
- if (!rem_wakeup) {
+ if (!rem_wakeup)
dwc_udelay(50);
- }
/* Deassert Reset core */
gpwrdn.d32 = 0;
*/
do {
gintsts_data_t gintsts;
- gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+ gintsts.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
if (gintsts.b.restoredone) {
gintsts.d32 = 0;
gintsts.b.restoredone = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
- DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
+ DWC_WRITE_REG32(&core_if->core_global_regs->
+ gintsts, gintsts.d32);
+ DWC_DEBUGPL(DBG_HCD,
+ "Restore Done Interrupt seen\n");
break;
}
dwc_udelay(10);
} while (--timeout);
- if (!timeout) {
+ if (!timeout)
DWC_WARN("Restore Done interrupt wasn't generated\n");
- }
}
- /* Set the flag's value to 0 again after receiving restore done interrupt */
+ /* Set the flag's value to 0 again after
+ * receiving restore done interrupt */
core_if->hibernation_suspend = 0;
/* This step is not described in functional spec but if not wait for this
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
DWC_PRINTF("Resume Starts Now\n");
- if (!reset) { // Indicates it is Resume Operation
+ if (!reset) {
+ /* Indicates it is Resume Operation */
hprt0.d32 = core_if->hr_backup->hprt0_local;
hprt0.b.prtres = 1;
hprt0.b.prtpwr = 1;
dwc_mdelay(100);
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
- } else { // Indicates it is Reset Operation
+ } else {
+ /* Indicates it is Reset Operation */
hprt0.d32 = core_if->hr_backup->hprt0_local;
hprt0.b.prtrst = 1;
hprt0.b.prtpwr = 1;
}
/** Saves some register values into system memory. */
-int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
+int dwc_otg_save_global_regs(dwc_otg_core_if_t *core_if)
{
struct dwc_otg_global_regs_backup *gr;
int i;
gr = core_if->gr_backup;
if (!gr) {
gr = DWC_ALLOC(sizeof(*gr));
- if (!gr) {
+ if (!gr)
return -DWC_E_NO_MEMORY;
- }
core_if->gr_backup = gr;
}
gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
- gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
- gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
+ gr->gnptxfsiz_local =
+ DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
+ gr->hptxfsiz_local =
+ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
#ifdef CONFIG_USB_DWC_OTG_LPM
gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
#endif
#endif
DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
- DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
+ DWC_DEBUGPL(DBG_ANY, "Backed up gdfifocfg = %08x\n",
+ gr->gdfifocfg_local);
return 0;
}
/** Saves GINTMSK register before setting the msk bits. */
-int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
+int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t *core_if)
{
struct dwc_otg_global_regs_backup *gr;
gr = core_if->gr_backup;
if (!gr) {
gr = DWC_ALLOC(sizeof(*gr));
- if (!gr) {
+ if (!gr)
return -DWC_E_NO_MEMORY;
- }
core_if->gr_backup = gr;
}
gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
- DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
+ DWC_DEBUGPL(DBG_ANY,
+ "=============Backing GINTMSK registers============\n");
DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
return 0;
}
-int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
+int dwc_otg_save_dev_regs(dwc_otg_core_if_t *core_if)
{
struct dwc_otg_dev_regs_backup *dr;
int i;
dr = core_if->dr_backup;
if (!dr) {
dr = DWC_ALLOC(sizeof(*dr));
- if (!dr) {
+ if (!dr)
return -DWC_E_NO_MEMORY;
- }
core_if->dr_backup = dr;
}
return 0;
}
-int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
+int dwc_otg_save_host_regs(dwc_otg_core_if_t *core_if)
{
struct dwc_otg_host_regs_backup *hr;
int i;
hr = core_if->hr_backup;
if (!hr) {
hr = DWC_ALLOC(sizeof(*hr));
- if (!hr) {
+ if (!hr)
return -DWC_E_NO_MEMORY;
- }
core_if->hr_backup = hr;
}
return 0;
}
-int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if)
+int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
{
struct dwc_otg_global_regs_backup *gr;
int i;
gr = core_if->gr_backup;
- if (!gr) {
+ if (!gr)
return -DWC_E_INVALID;
- }
DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
return 0;
}
-int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
+int dwc_otg_restore_dev_regs(dwc_otg_core_if_t *core_if, int rem_wakeup)
{
struct dwc_otg_dev_regs_backup *dr;
int i;
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
dr->dctl);
}
-
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
+
+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
+ dr->daintmsk);
+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
+ dr->diepmsk);
+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
+ dr->doepmsk);
for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz,
+ dr->dieptsiz[i]);
+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma,
+ dr->diepdma[i]);
+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl,
+ dr->diepctl[i]);
}
return 0;
}
-int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
+int dwc_otg_restore_host_regs(dwc_otg_core_if_t *core_if, int reset)
{
struct dwc_otg_host_regs_backup *hr;
int i;
hr = core_if->hr_backup;
- if (!hr) {
+ if (!hr)
return -DWC_E_INVALID;
- }
- DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
- //if (!reset)
- //{
- // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
- //}
+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
+ hr->hcfg_local);
+ /* if (!reset)
+ * {
+ * DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir,
+ * hr->hfir_local);
+ * }
+ */
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
hr->haintmsk_local);
return 0;
}
-int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
+int restore_lpm_i2c_regs(dwc_otg_core_if_t *core_if)
{
struct dwc_otg_global_regs_backup *gr;
return 0;
}
-int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
+int restore_essential_regs(dwc_otg_core_if_t *core_if, int rmode, int is_host)
{
struct dwc_otg_global_regs_backup *gr;
pcgcctl_data_t pcgcctl = {.d32 = 0 };
DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
dwc_udelay(10);
- /* Load restore values for [31:14] bits and set EssRegRestored bit */
+ /* Load restore values for [31:14] bits
+ * and set EssRegRestored bit */
pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
pcgcctl.b.ess_reg_restored = 1;
} else {
dcfg_data_t dcfg = {.d32 = 0 };
dcfg.d32 = core_if->dr_backup->dcfg;
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
+ dcfg.d32);
/* Load restore values for [31:14] bits */
pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
- if (!rmode) {
+ if (!rmode)
pcgcctl.d32 |= 0x208;
- }
DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
dwc_udelay(10);
* Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
* type.
*/
-static void init_fslspclksel(dwc_otg_core_if_t * core_if)
+static void init_fslspclksel(dwc_otg_core_if_t *core_if)
{
uint32_t val;
hcfg_data_t hcfg;
* Initializes the DevSpd field of the DCFG register depending on the PHY type
* and the enumeration speed of the device.
*/
-static void init_devspd(dwc_otg_core_if_t * core_if)
+static void init_devspd(dwc_otg_core_if_t *core_if)
{
uint32_t val;
dcfg_data_t dcfg;
*
* @param core_if Programming view of the DWC_otg controller
*/
-static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
+static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
{
uint32_t num_in_eps = 0;
uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
hwcfg1 >>= 2;
}
- if (core_if->hwcfg4.b.ded_fifo_en) {
- num_in_eps =
- (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
- }
+ if (core_if->hwcfg4.b.ded_fifo_en) {
+ num_in_eps =
+ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
+ }
+
+ return num_in_eps;
+}
+
+/**
+ * This function calculates the number of OUT EPS
+ * using GHWCFG1 and GHWCFG2 registers values
+ *
+ * @param core_if Programming view of the DWC_otg controller
+ */
+static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
+{
+ uint32_t num_out_eps = 0;
+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
+ int i;
+
+ for (i = 0; i < num_eps; ++i) {
+ if (!(hwcfg1 & 0x1))
+ num_out_eps++;
+
+ hwcfg1 >>= 2;
+ }
+ return num_out_eps;
+}
+
+void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
+{
+ int i = 0;
+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
+ gusbcfg_data_t usbcfg = {.d32 = 0 };
+ gi2cctl_data_t i2cctl = {.d32 = 0 };
+
+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
+ /* Common Initialization */
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+
+ /* Program the ULPI External VBUS bit if needed */
+ usbcfg.b.ulpi_ext_vbus_drv =
+ (core_if->core_params->phy_ulpi_ext_vbus ==
+ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
+
+ /* Set external TS Dline pulsing */
+ usbcfg.b.term_sel_dl_pulse =
+ (core_if->core_params->ts_dline == 1) ? 1 : 0;
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+
+ /* Reset the Controller */
+ dwc_otg_core_reset(core_if);
+
+ core_if->adp_enable = core_if->core_params->adp_supp_enable;
+ core_if->power_down = core_if->core_params->power_down;
+
+ /* Initialize parameters from Hardware configuration registers. */
+ dev_if->num_in_eps = calc_num_in_eps(core_if);
+ dev_if->num_out_eps = calc_num_out_eps(core_if);
+
+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
+ core_if->hwcfg4.b.num_dev_perio_in_ep);
+
+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+ dev_if->perio_tx_fifo_size[i] =
+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
+ i, dev_if->perio_tx_fifo_size[i]);
+ }
+
+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+ dev_if->tx_fifo_size[i] =
+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
+ i, dev_if->tx_fifo_size[i]);
+ }
+
+ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
+ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
+ core_if->nperio_tx_fifo_size =
+ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
+
+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
+ core_if->nperio_tx_fifo_size);
+
+ /* This programming sequence needs to happen in FS mode before any other
+ * programming occurs */
+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+ /* If FS mode with FS PHY */
+
+ /* core_init() is now called on every switch so only call the
+ * following for the first time through. */
+ if (!core_if->phy_init_done) {
+ core_if->phy_init_done = 1;
+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+ usbcfg.b.physel = 1;
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+
+ /* Reset after a PHY select */
+ dwc_otg_core_reset(core_if);
+ }
+
+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
+ * do this on HNP Dev/Host mode switches (done in dev_init and
+ * host_init). */
+ if (dwc_otg_is_host_mode(core_if))
+ init_fslspclksel(core_if);
+ else
+ init_devspd(core_if);
+
+ if (core_if->core_params->i2c_enable) {
+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+ usbcfg.b.otgutmifssel = 1;
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+
+ /* Program GI2CCTL.I2CEn */
+ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
+ i2cctl.b.i2cdevaddr = 1;
+ i2cctl.b.i2cen = 0;
+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
+ i2cctl.b.i2cen = 1;
+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
+ }
+
+ } /* endif speed == DWC_SPEED_PARAM_FULL */
+ else {
+ /* High speed PHY. */
+ if (!core_if->phy_init_done) {
+ core_if->phy_init_done = 1;
+ /* HS PHY parameters. These parameters are preserved
+ * during soft reset so only program the first time. Do
+ * a soft reset immediately after setting phyif. */
+
+ if (core_if->core_params->phy_type == 2) {
+ /* ULPI interface */
+ usbcfg.b.ulpi_utmi_sel = 1;
+ usbcfg.b.phyif = 0;
+ usbcfg.b.ddrsel =
+ core_if->core_params->phy_ulpi_ddr;
+ } else if (core_if->core_params->phy_type == 1) {
+ /* UTMI+ interface */
+ usbcfg.b.ulpi_utmi_sel = 0;
+ if (core_if->core_params->phy_utmi_width == 16)
+ usbcfg.b.phyif = 1;
+ else
+ usbcfg.b.phyif = 0;
+ } else {
+ DWC_ERROR("FS PHY TYPE\n");
+ }
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+ /* Reset after setting the PHY parameters */
+ dwc_otg_core_reset(core_if);
+ }
+ }
+
+ if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
+ (core_if->core_params->ulpi_fs_ls)) {
+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+ usbcfg.b.ulpi_fsls = 1;
+ usbcfg.b.ulpi_clk_sus_m = 1;
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+ } else {
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+ usbcfg.b.ulpi_fsls = 0;
+ usbcfg.b.ulpi_clk_sus_m = 0;
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+ }
+
+ /* Program the GAHBCFG Register. */
+ switch (core_if->hwcfg2.b.architecture) {
+
+ case DWC_SLAVE_ONLY_ARCH:
+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
+ ahbcfg.b.nptxfemplvl_txfemplvl =
+ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+ core_if->dma_enable = 0;
+ core_if->dma_desc_enable = 0;
+ break;
+
+ case DWC_EXT_DMA_ARCH:
+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
+ {
+ uint8_t brst_sz = core_if->core_params->dma_burst_size;
+ ahbcfg.b.hburstlen = 0;
+ while (brst_sz > 1) {
+ ahbcfg.b.hburstlen++;
+ brst_sz >>= 1;
+ }
+ }
+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+ core_if->dma_desc_enable =
+ (core_if->core_params->dma_desc_enable != 0);
+ break;
+
+ case DWC_INT_DMA_ARCH:
+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
+ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
+ Host mode ISOC in issue fix - vahrama */
+ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+ core_if->dma_desc_enable =
+ (core_if->core_params->dma_desc_enable != 0);
+ break;
+
+ }
+ if (core_if->dma_enable) {
+ if (core_if->dma_desc_enable)
+ DWC_PRINTF("Using Descriptor DMA mode\n");
+ else
+ DWC_PRINTF("Using Buffer DMA mode\n");
+ } else {
+ DWC_PRINTF("Using Slave mode\n");
+ core_if->dma_desc_enable = 0;
+ }
+
+ if (core_if->core_params->ahb_single)
+ ahbcfg.b.ahbsingle = 1;
+
+ ahbcfg.b.dmaenable = core_if->dma_enable;
+ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
+
+ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
+
+ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
+ core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
+ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
+ ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
+ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
+ ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
+
+ /*
+ * Program the GUSBCFG register.
+ */
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+
+ switch (core_if->hwcfg2.b.op_mode) {
+ case DWC_MODE_HNP_SRP_CAPABLE:
+ usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+ break;
+
+ case DWC_MODE_SRP_ONLY_CAPABLE:
+ usbcfg.b.hnpcap = 0;
+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+ break;
+
+ case DWC_MODE_NO_HNP_SRP_CAPABLE:
+ usbcfg.b.hnpcap = 0;
+ usbcfg.b.srpcap = 0;
+ break;
+
+ case DWC_MODE_SRP_CAPABLE_DEVICE:
+ usbcfg.b.hnpcap = 0;
+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+ break;
+
+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
+ usbcfg.b.hnpcap = 0;
+ usbcfg.b.srpcap = 0;
+ break;
+
+ case DWC_MODE_SRP_CAPABLE_HOST:
+ usbcfg.b.hnpcap = 0;
+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+ break;
+
+ case DWC_MODE_NO_SRP_CAPABLE_HOST:
+ usbcfg.b.hnpcap = 0;
+ usbcfg.b.srpcap = 0;
+ break;
+ }
+
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+ if (core_if->core_params->lpm_enable) {
+ glpmcfg_data_t lpmcfg = {.d32 = 0 };
+
+ /* To enable LPM support set lpm_cap_en bit */
+ lpmcfg.b.lpm_cap_en = 1;
+
+ /* Make AppL1Res ACK */
+ lpmcfg.b.appl_resp = 1;
+
+ /* Retry 3 times */
+ lpmcfg.b.retry_count = 3;
- return num_in_eps;
-}
+ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
+ 0, lpmcfg.d32);
-/**
- * This function calculates the number of OUT EPS
- * using GHWCFG1 and GHWCFG2 registers values
- *
- * @param core_if Programming view of the DWC_otg controller
- */
-static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
-{
- uint32_t num_out_eps = 0;
- uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
- uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
- int i;
+ }
+#endif
+ if (core_if->core_params->ic_usb_cap) {
+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
+ gusbcfg.b.ic_usb_cap = 1;
+ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
+ 0, gusbcfg.d32);
+ }
+ {
+ gotgctl_data_t gotgctl = {.d32 = 0 };
+ gotgctl.b.otgver = core_if->core_params->otg_ver;
+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
+ gotgctl.d32);
+ /* Set OTG version supported */
+ core_if->otg_ver = core_if->core_params->otg_ver;
+ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
+ core_if->core_params->otg_ver, core_if->otg_ver);
+ }
- for (i = 0; i < num_eps; ++i) {
- if (!(hwcfg1 & 0x1))
- num_out_eps++;
+ /* Enable common interrupts */
+ dwc_otg_enable_common_interrupts(core_if);
- hwcfg1 >>= 2;
+ /* Do device or host intialization based on mode during PCD
+ * and HCD initialization */
+ if (dwc_otg_is_host_mode(core_if)) {
+ DWC_PRINTF("^^^^^^^^^^^^^^^^^^Host Mode\n");
+ core_if->op_state = A_HOST;
+ } else {
+ DWC_PRINTF("^^^^^^^^^^^^^^^^^Device Mode\n");
+ core_if->op_state = B_PERIPHERAL;
+#ifdef DWC_DEVICE_ONLY
+ dwc_otg_core_dev_init(core_if);
+#endif
}
- return num_out_eps;
}
/**
* @param core_if Programming view of the DWC_otg controller
*
*/
-void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
+void dwc_otg_core_init_no_reset(dwc_otg_core_if_t *core_if)
{
int i = 0;
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
gi2cctl_data_t i2cctl = {.d32 = 0 };
DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
-
/* Common Initialization */
usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
/* Reset the Controller */
- dwc_otg_core_reset(core_if);
+ /* dwc_otg_core_reset(core_if); */
core_if->adp_enable = core_if->core_params->adp_supp_enable;
core_if->power_down = core_if->core_params->power_down;
DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
/* Reset after a PHY select */
- dwc_otg_core_reset(core_if);
+ /* dwc_otg_core_reset(core_if); */
}
- /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
* do this on HNP Dev/Host mode switches (done in dev_init and
* host_init). */
- if (dwc_otg_is_host_mode(core_if)) {
+ if (dwc_otg_is_host_mode(core_if))
init_fslspclksel(core_if);
- } else {
+ else
init_devspd(core_if);
- }
if (core_if->core_params->i2c_enable) {
DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
} else if (core_if->core_params->phy_type == 1) {
/* UTMI+ interface */
usbcfg.b.ulpi_utmi_sel = 0;
- if (core_if->core_params->phy_utmi_width == 16) {
+ if (core_if->core_params->phy_utmi_width == 16)
usbcfg.b.phyif = 1;
-
- } else {
+ else
usbcfg.b.phyif = 0;
- }
} else {
DWC_ERROR("FS PHY TYPE\n");
}
DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
/* Reset after setting the PHY parameters */
- dwc_otg_core_reset(core_if);
+ /* dwc_otg_core_reset(core_if); */
}
}
case DWC_INT_DMA_ARCH:
DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
- /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
+ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
Host mode ISOC in issue fix - vahrama */
- ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR16;
+ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
core_if->dma_enable = (core_if->core_params->dma_enable != 0);
core_if->dma_desc_enable =
(core_if->core_params->dma_desc_enable != 0);
}
if (core_if->dma_enable) {
- if (core_if->dma_desc_enable) {
+ if (core_if->dma_desc_enable)
DWC_PRINTF("Using Descriptor DMA mode\n");
- } else {
+ else
DWC_PRINTF("Using Buffer DMA mode\n");
- }
} else {
DWC_PRINTF("Using Slave mode\n");
core_if->dma_desc_enable = 0;
}
- if (core_if->core_params->ahb_single) {
+ if (core_if->core_params->ahb_single)
ahbcfg.b.ahbsingle = 1;
- }
ahbcfg.b.dmaenable = core_if->dma_enable;
DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
/* Do device or host intialization based on mode during PCD
* and HCD initialization */
if (dwc_otg_is_host_mode(core_if)) {
- DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
+ DWC_PRINTF("^^^^^^^^^^^^^^^^^^Host Mode\n");
core_if->op_state = A_HOST;
} else {
- DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
+ DWC_PRINTF("^^^^^^^^^^^^^^^^^Device Mode\n");
core_if->op_state = B_PERIPHERAL;
#ifdef DWC_DEVICE_ONLY
dwc_otg_core_dev_init(core_if);
*
* @param core_if Programming view of DWC_otg controller
*/
-void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
{
gintmsk_data_t intr_mask = {.d32 = 0 };
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
intr_mask.b.erlysuspend = 1;
- if (core_if->en_multiple_tx_fifo == 0) {
+ if (core_if->en_multiple_tx_fifo == 0)
intr_mask.b.epmismatch = 1;
- }
- //intr_mask.b.incomplisoout = 1;
+ /* intr_mask.b.incomplisoout = 1; */
intr_mask.b.incomplisoin = 1;
/* Enable the ignore frame number for ISOC xfers - MAS */
if (core_if->dma_desc_enable) {
dctl_data_t dctl1 = {.d32 = 0 };
dctl1.b.ifrmnum = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
- dctl, 0, dctl1.d32);
+ DWC_MODIFY_REG32(&core_if->dev_if->
+ dev_global_regs->dctl, 0, dctl1.d32);
DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
- DWC_READ_REG32(&core_if->dev_if->
- dev_global_regs->dctl));
+ DWC_READ_REG32(&core_if->
+ dev_if->dev_global_regs->
+ dctl));
}
}
#endif
if (core_if->pti_enh_enable) {
dctl_data_t dctl = {.d32 = 0 };
dctl.b.ifrmnum = 1;
- DWC_MODIFY_REG32(&core_if->
- dev_if->dev_global_regs->dctl,
- 0, dctl.d32);
+ DWC_MODIFY_REG32(&core_if->dev_if->
+ dev_global_regs->dctl, 0,
+ dctl.d32);
} else {
intr_mask.b.incomplisoin = 1;
intr_mask.b.incomplisoout = 1;
* @param core_if Programming view of DWC_otg controller
*
*/
-void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
+void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
{
int i;
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
fifosize_data_t txfifosize;
dthrctl_data_t dthrctl;
fifosize_data_t ptxfifosize;
-// uint16_t rxfsiz, nptxfsiz;
-// gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-// hwcfg3_data_t hwcfg3 = {.d32 = 0 };
+ /* uint16_t rxfsiz, nptxfsiz; */
+ /* gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; */
+ /* hwcfg3_data_t hwcfg3 = {.d32 = 0 }; */
gotgctl_data_t gotgctl = {.d32 = 0 };
- gahbcfg_data_t gahbcfg = {.d32 = 0};
-
+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
+
/* Restart the Phy Clock */
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
dwc_udelay(10);
- gahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR16;
- DWC_MODIFY_REG32(&global_regs->gahbcfg, 0 , gahbcfg.b.hburstlen);
+ gahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
+ DWC_MODIFY_REG32(&global_regs->gahbcfg, 0, gahbcfg.d32);
/* Device configuration register */
init_devspd(core_if);
dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
/* Enable Device OUT NAK in case of DDMA mode */
- if (core_if->core_params->dev_out_nak) {
+ if (core_if->core_params->dev_out_nak)
dcfg.b.endevoutnak = 1;
- }
if (core_if->core_params->cont_on_bna) {
dctl_data_t dctl = {.d32 = 0 };
if (core_if->otg_ver) {
core_if->otg_sts = 0;
gotgctl.b.devhnpen = 1;
- DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, gotgctl.d32, 0);
+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
+ gotgctl.d32, 0);
}
-
+
DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
/* Configure data FIFO sizes */
-
+
if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
#ifdef DWC_UTE_CFI
core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
/** Set Tx FIFO Mask all bits 0 */
core_if->tx_msk = 0;
- /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
+ /* core_if->en_multiple_tx_fifo equals
+ * core_if->hwcfg4.b.ded_fifo_en,
* and ded_fifo_en is 1 in default*/
if (core_if->en_multiple_tx_fifo == 0) {
/* Non-periodic Tx FIFO */
/** @todo Finish debug of this */
ptxfifosize.b.startaddr =
nptxfifosize.b.startaddr + nptxfifosize.b.depth;
- for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep;
+ i++) {
ptxfifosize.b.depth =
params->dev_perio_tx_fifo_size[i];
DWC_DEBUGPL(DBG_CIL,
"initial dtxfsiz[%d]=%08x\n", i,
- DWC_READ_REG32(&global_regs->dtxfsiz
- [i]));
+ DWC_READ_REG32(&global_regs->
+ dtxfsiz[i]));
DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
ptxfifosize.d32);
DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
i,
- DWC_READ_REG32(&global_regs->dtxfsiz
- [i]));
+ DWC_READ_REG32(&global_regs->
+ dtxfsiz[i]));
ptxfifosize.b.startaddr += ptxfifosize.b.depth;
}
} else {
txfifosize.b.startaddr += txfifosize.b.depth;
}
- #if 0
- /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO
- * Before 3.00a EpInfoBase was being configured in ep enable/disable
+#if 0
+ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO
+ * Before 3.00a EpInfoBase was being configured in ep enable/disable
* routine as well. Starting from 3.00a it will be set to the end of
* allocated FIFO space here due to ep 0 OUT always keeping enabled
*/
gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
- gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
+ gdfifocfg.b.gdfifocfg =
+ (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
- rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
- nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
+ rxfsiz =
+ (DWC_READ_REG32(&global_regs->grxfsiz) &
+ 0x0000ffff);
+ nptxfsiz =
+ (DWC_READ_REG32(&global_regs->gnptxfsiz) >>
+ 16);
gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
} else {
gdfifocfg.b.epinfobase = txfifosize.b.startaddr;
}
- //DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
- #endif
+ /* DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); */
+#endif
}
}
if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
core_if->start_predict = 0;
- for (i = 0; i <= core_if->dev_if->num_in_eps; ++i) {
- core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
- }
+ for (i = 0; i <= core_if->dev_if->num_in_eps; ++i)
+ core_if->nextep_seq[i] = 0xff; /* 0xff - EP not active */
core_if->nextep_seq[0] = 0;
core_if->first_in_nextep_seq = 0;
diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
diepctl.b.nextep = 0;
DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
- /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
+ /* Update IN Endpoint Mismatch Count
+ * by active IN NP EP count + 1 */
dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
dcfg.b.epmscnt = 2;
DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
DWC_DEBUGPL(DBG_CILV,
"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
__func__, core_if->first_in_nextep_seq);
- for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++)
DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
- }
DWC_DEBUGPL(DBG_CILV, "\n");
}
- /* Clear all pending Device Interrupts */
- /** @todo - if the condition needed to be checked
- * or in any case all pending interrutps should be cleared?
- */
+ /* Clear all pending Device Interrupts
+ * @todo - if the condition needed to be checked
+ * or in any case all pending interrutps should be cleared?
+ */
if (core_if->multiproc_int_enable) {
for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
- DWC_WRITE_REG32(&dev_if->dev_global_regs->
- diepeachintmsk[i], 0);
+ DWC_WRITE_REG32(&dev_if->
+ dev_global_regs->diepeachintmsk[i], 0);
}
for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
- DWC_WRITE_REG32(&dev_if->dev_global_regs->
- doepeachintmsk[i], 0);
+ DWC_WRITE_REG32(&dev_if->
+ dev_global_regs->doepeachintmsk[i], 0);
}
DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
gintmsk_data_t gintsts = {.d32 = 0 };
doepint_data_t doepint = {.d32 = 0 };
dctl.b.sgoutnak = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+ dctl, 0, dctl.d32);
do {
j++;
dwc_udelay(10);
- gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+ gintsts.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->
+ gintsts);
if (j == 100000) {
- DWC_ERROR("SNAK as not set during 10s\n");
+ DWC_ERROR
+ ("SNAK as not set during 10s\n");
break;
}
} while (!gintsts.b.goutnakeff);
gintsts.d32 = 0;
gintsts.b.goutnakeff = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,
+ gintsts.d32);
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
j = 0;
- DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
+ doepctl, depctl.d32);
do {
dwc_udelay(10);
- doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[i]->doepint);
- if (j == 100000) {
- DWC_ERROR("EPDIS was not set during 10s\n");
+ doepint.d32 =
+ DWC_READ_REG32(&core_if->
+ dev_if->out_ep_regs[i]->
+ doepint);
+ if (j++ >= 10000) {
+ DWC_ERROR
+ ("EPDIS was not set during 1s\n");
break;
}
} while (!doepint.b.epdisabled);
doepint.b.epdisabled = 1;
- DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
+ doepint, doepint.d32);
dctl.d32 = 0;
dctl.b.cgoutnak = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+ dctl, 0, dctl.d32);
} else {
depctl.d32 = 0;
}
diepmsk_data_t msk = {.d32 = 0 };
msk.b.txfifoundrn = 1;
if (core_if->multiproc_int_enable) {
- DWC_MODIFY_REG32(&dev_if->dev_global_regs->
- diepeachintmsk[0], msk.d32, msk.d32);
+ DWC_MODIFY_REG32(&dev_if->
+ dev_global_regs->diepeachintmsk[0],
+ msk.d32, msk.d32);
} else {
DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
msk.d32, msk.d32);
*
* @param core_if Programming view of DWC_otg controller
*/
-void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
gintmsk_data_t intr_mask = {.d32 = 0 };
*
* @param core_if Programming view of DWC_otg controller
*/
-void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
gintmsk_data_t intr_mask = {.d32 = 0 };
intr_mask.b.nptxfempty = 1;
DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
+ /* Clear pending interrupts */
+ DWC_WRITE_REG32(&global_regs->gintsts, intr_mask.d32);
}
/**
* @param core_if Programming view of DWC_otg controller
*
*/
-void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
+void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
dwc_otg_host_if_t *host_if = core_if->host_if;
hprt0_data_t hprt0 = {.d32 = 0 };
fifosize_data_t nptxfifosize;
fifosize_data_t ptxfifosize;
-// uint16_t rxfsiz, nptxfsiz, hptxfsiz;
-// gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
+ /* uint16_t rxfsiz, nptxfsiz, hptxfsiz; */
+ /* gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; */
int i;
hcchar_data_t hcchar;
hcfg_data_t hcfg;
struct dwc_otg_platform_data *pldata;
pldata = core_if->otg_dev->pldata;
-
-
DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
dwc_udelay(10);
-
- if ((core_if->otg_ver == 1) && (core_if->op_state == A_HOST)) {
- DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
+
+ if ((core_if->otg_ver == 1) && (core_if->op_state == A_HOST)) {
+ DWC_PRINTF("Init: Port Power? op_state=%d\n",
+ core_if->op_state);
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
if (hprt0.b.prtpwr == 0) {
}
/* This bit allows dynamic reloading of the HFIR register
- * during runtime. This bit needs to be programmed during
+ * during runtime. This bit needs to be programmed during
* initial configuration and its value must not be changed
* during runtime.*/
if (core_if->core_params->reload_ctl == 1) {
/* Rx FIFO */
DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
DWC_READ_REG32(&global_regs->grxfsiz));
- DWC_WRITE_REG32(&global_regs->grxfsiz, 0x0200);//params->host_rx_fifo_size);
+ /* params->host_rx_fifo_size */
+ DWC_WRITE_REG32(&global_regs->grxfsiz, 0x0200);
DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
DWC_READ_REG32(&global_regs->grxfsiz));
/* Non-periodic Tx FIFO */
DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
DWC_READ_REG32(&global_regs->gnptxfsiz));
- nptxfifosize.b.depth = 0x0080;//params->host_nperio_tx_fifo_size;
- nptxfifosize.b.startaddr = 0x0200;//params->host_rx_fifo_size;
+ /* params->host_nperio_tx_fifo_size */
+ nptxfifosize.b.depth = 0x0080;
+ /* params->host_rx_fifo_size */
+ nptxfifosize.b.startaddr = 0x0200;
DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
DWC_READ_REG32(&global_regs->gnptxfsiz));
/* Periodic Tx FIFO */
DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
DWC_READ_REG32(&global_regs->hptxfsiz));
- ptxfifosize.b.depth = 0x0100;//params->host_perio_tx_fifo_size;
- ptxfifosize.b.startaddr = 0x0280;//nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+ /* params->host_perio_tx_fifo_size */
+ ptxfifosize.b.depth = 0x0100;
+ /* nptxfifosize.b.startaddr + nptxfifosize.b.depth */
+ ptxfifosize.b.startaddr = 0x0280;
DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
DWC_READ_REG32(&global_regs->hptxfsiz));
- #if 0
+#if 0
/* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
* and ded_fifo_en is 1 in default
*/
if (core_if->en_multiple_tx_fifo) {
- /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
+ /* Global DFIFOCFG calculation for Host mode
+ * - include RxFIFO, NPTXFIFO and HPTXFIFO */
gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
- rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
- nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
- hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
+ rxfsiz =
+ (DWC_READ_REG32(&global_regs->grxfsiz) &
+ 0x0000ffff);
+ nptxfsiz =
+ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
+ hptxfsiz =
+ (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
}
- #endif
+#endif
}
/* TODO - check this */
/* Clear Host Set HNP Enable in the OTG Control Register */
gotgctl.b.hstsethnpen = 1;
DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
- /* Make sure the FIFOs are flushed. */
- dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
+ /* Make sure the FIFOs are flushed
+ * all TX FIFOs */
+ dwc_otg_flush_tx_fifo(core_if, 0x10);
dwc_otg_flush_rx_fifo(core_if);
/* Clear Host Set HNP Enable in the OTG Control Register */
hcchar.b.chdis = 1;
hcchar.b.epdir = 0;
DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
- DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__,
+ i);
do {
hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
if (++count > 1000) {
hprt0.b.prtpwr = 1;
DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
}
- if(pldata->power_enable)
- pldata->power_enable(1);
+ if (pldata->power_enable)
+ pldata->power_enable(1);
}
dwc_otg_enable_host_interrupts(core_if);
* @param core_if Programming view of DWC_otg controller
* @param hc Information needed to initialize the host channel
*/
-void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
uint32_t intr_enable;
hcintmsk_data_t hc_intr_mask;
hc_intr_mask.d32 = 0;
hc_intr_mask.b.chhltd = 1;
if (core_if->dma_enable) {
- /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
+ /* For Descriptor DMA mode core halts the channel
+ * on AHB error. Interrupt is not required */
if (!core_if->dma_desc_enable)
hc_intr_mask.b.ahberr = 1;
else {
hc_intr_mask.b.ack = 1;
if (hc->ep_is_in) {
hc_intr_mask.b.datatglerr = 1;
- if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR)
hc_intr_mask.b.nak = 1;
- }
}
}
} else {
} else {
hc_intr_mask.b.nak = 1;
hc_intr_mask.b.nyet = 1;
- if (hc->do_ping) {
+ if (hc->do_ping)
hc_intr_mask.b.ack = 1;
- }
}
if (hc->do_split) {
hc_intr_mask.b.nak = 1;
- if (hc->complete_split) {
+ if (hc->complete_split)
hc_intr_mask.b.nyet = 1;
- } else {
+ else
hc_intr_mask.b.ack = 1;
- }
}
- if (hc->error_state) {
+ if (hc->error_state)
hc_intr_mask.b.ack = 1;
- }
break;
case DWC_OTG_EP_TYPE_INTR:
hc_intr_mask.b.xfercompl = 1;
hc_intr_mask.b.datatglerr = 1;
hc_intr_mask.b.frmovrun = 1;
- if (hc->ep_is_in) {
+ if (hc->ep_is_in)
hc_intr_mask.b.bblerr = 1;
- }
- if (hc->error_state) {
+ if (hc->error_state)
hc_intr_mask.b.ack = 1;
- }
if (hc->do_split) {
- if (hc->complete_split) {
+ if (hc->complete_split)
hc_intr_mask.b.nyet = 1;
- } else {
+ else
hc_intr_mask.b.ack = 1;
- }
}
break;
case DWC_OTG_EP_TYPE_ISOC:
* @param hc Host channel to halt.
* @param halt_status Reason for halting the channel.
*/
-void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
- dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
+void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
+ dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
{
gnptxsts_data_t nptxsts;
hptxsts_data_t hptxsts;
hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
- /* No need to set the bit in DDMA for disabling the channel */
- //TODO check it everywhere channel is disabled
+ /* No need to set the bit in DDMA for disabling the channel
+ * TODO check it everywhere channel is disabled */
if (!core_if->core_params->dma_desc_enable)
hcchar.b.chen = 1;
hcchar.b.chdis = 1;
if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
- if (nptxsts.b.nptxqspcavail == 0) {
+ if (nptxsts.b.nptxqspcavail == 0)
hcchar.b.chen = 0;
- }
} else {
hptxsts.d32 =
DWC_READ_REG32(&host_global_regs->hptxsts);
* @param core_if Programming view of DWC_otg controller.
* @param hc Identifies the host channel to clean up.
*/
-void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
dwc_otg_hc_regs_t *hc_regs;
* @param hcchar Current value of the HCCHAR register for the specified host
* channel.
*/
-static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
- dwc_hc_t * hc, hcchar_data_t * hcchar)
+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
+ dwc_hc_t *hc, hcchar_data_t *hcchar)
{
if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
}
- if (!gintsts.b.goutnakeff) {
+ if (!gintsts.b.goutnakeff)
dctl.b.sgoutnak = 1;
- }
+
DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
dctl.d32);
}
-void set_pid_isoc(dwc_hc_t * hc)
+void set_pid_isoc(dwc_hc_t *hc)
{
/* Set up the initial PID for the transfer. */
if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
if (hc->ep_is_in) {
- if (hc->multi_count == 1) {
+ if (hc->multi_count == 1)
hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
- } else if (hc->multi_count == 2) {
+ else if (hc->multi_count == 2)
hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
- } else {
+ else
hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
- }
} else {
- if (hc->multi_count == 1) {
+ if (hc->multi_count == 1)
hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
- } else {
+ else
hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
- }
}
} else {
hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
* PktCnt fields in the HCTSIZn register. The multi_count value may be changed
* to reflect the final xfer_len value.
*/
-void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
hcchar_data_t hcchar;
hctsiz_data_t hctsiz;
*/
uint32_t max_periodic_len =
hc->multi_count * hc->max_packet;
- if (hc->xfer_len > max_periodic_len) {
+ if (hc->xfer_len > max_periodic_len)
hc->xfer_len = max_periodic_len;
- } else {
- }
} else if (hc->xfer_len > max_hc_xfer_size) {
- /* Make sure that xfer_len is a multiple of max packet size. */
+ /* Make sure that xfer_len is a
+ * multiple of max packet size. */
hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
}
if (core_if->dma_enable) {
dwc_dma_t dma_addr;
- if (hc->align_buff) {
+ if (hc->align_buff)
dma_addr = hc->align_buff;
- } else {
+ else
dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
- }
DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
}
* @param core_if Programming view of DWC_otg controller.
* @param hc Information needed to initialize the host channel.
*/
-void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
hcchar_data_t hcchar;
/* Packet Count and Xfer Size are not used in Descriptor DMA mode */
hctsiz.b_ddma.pid = hc->data_pid_start;
- hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
- hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
+ /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
+ hctsiz.b_ddma.ntd = hc->ntd - 1;
+ /* Non-zero only for high-speed interrupt endpoints */
+ hctsiz.b_ddma.schinfo = hc->schinfo;
DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
* @return 1 if a new request is queued, 0 if no more requests are required
* for this transfer.
*/
-int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
* Starts a PING transfer. This function should only be called in Slave mode.
* The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
*/
-void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
hcchar_data_t hcchar;
hctsiz_data_t hctsiz;
* Upon return the xfer_buff and xfer_count fields in _hc are incremented by
* then number of bytes written to the Tx FIFO.
*/
-void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
{
uint32_t i;
uint32_t remaining_count;
uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
remaining_count = hc->xfer_len - hc->xfer_count;
- if (remaining_count > hc->max_packet) {
+ if (remaining_count > hc->max_packet)
byte_count = hc->max_packet;
- } else {
+ else
byte_count = remaining_count;
- }
dword_count = (byte_count + 3) / 4;
if ((((unsigned long)data_buff) & 0x3) == 0) {
/* xfer_buff is DWORD aligned. */
- for (i = 0; i < dword_count; i++, data_buff++) {
+ for (i = 0; i < dword_count; i++, data_buff++)
DWC_WRITE_REG32(data_fifo, *data_buff);
- }
} else {
/* xfer_buff is not DWORD aligned. */
for (i = 0; i < dword_count; i++, data_buff++) {
* Gets the current USB frame number. This is the frame number from the last
* SOF packet.
*/
-uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
{
dsts_data_t dsts;
dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
}
/**
- * Calculates and gets the frame Interval value of HFIR register according PHY
+ * Calculates and gets the frame Interval value of HFIR register according PHY
* type and speed.The application can modify a value of HFIR register only after
- * the Port Enable bit of the Host Port Control and Status register
+ * the Port Enable bit of the Host Port Control and Status register
* (HPRT.PrtEnaPort) has been set.
*/
-uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
+uint32_t calc_frame_interval(dwc_otg_core_if_t *core_if)
{
gusbcfg_data_t usbcfg;
hwcfg2_data_t hwcfg2;
hprt0_data_t hprt0;
- int clock = 60; // default value
+ int clock = 60; /* default value */
usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
* @param core_if Programming view of DWC_otg controller.
* @param dest Destination buffer for packet data.
*/
-void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
+void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
{
device_grxsts_data_t status;
/* Get the 8 bytes of a setup transaction data */
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP0 data.
*/
-void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
dsts_data_t dsts;
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to activate.
*/
-void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
depctl_data_t depctl;
depctl.b.eptype = ep->type;
depctl.b.txfnum = ep->tx_fifo_num;
- if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
- depctl.b.setd0pid = 1; // ???
- } else {
+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
depctl.b.setd0pid = 1;
- }
+ else
+ depctl.b.setd0pid = 1;
+
depctl.b.usbactep = 1;
/* Update nextep_seq array and EPMSCNT in DCFG */
- if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
+ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {/*NP IN EP*/
for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
- if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
+ if (core_if->nextep_seq[i] ==
+ core_if->first_in_nextep_seq)
break;
}
core_if->nextep_seq[i] = ep->num;
- core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
+ core_if->nextep_seq[ep->num] =
+ core_if->first_in_nextep_seq;
depctl.b.nextep = core_if->nextep_seq[ep->num];
- dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
+ dcfg.d32 =
+ DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
dcfg.b.epmscnt++;
- DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg,
+ dcfg.d32);
DWC_DEBUGPL(DBG_PCDV,
"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
}
-
DWC_WRITE_REG32(addr, depctl.d32);
DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
}
diepmsk.b.epdisabled = 1;
diepmsk.b.ahberr = 1;
diepmsk.b.intknepmis = 1;
- if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
+ if (!core_if->en_multiple_tx_fifo
+ && core_if->dma_enable)
diepmsk.b.intknepmis = 0;
- diepmsk.b.txfifoundrn = 1; //?????
- if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
+ diepmsk.b.txfifoundrn = 1;
+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
diepmsk.b.nak = 1;
- }
-/*
+ /*
if (core_if->dma_desc_enable) {
diepmsk.b.bna = 1;
}
-*/
-/*
+
if (core_if->dma_enable) {
doepmsk.b.nak = 1;
}
-*/
- DWC_WRITE_REG32(&dev_if->dev_global_regs->
- diepeachintmsk[ep->num], diepmsk.d32);
+ */
+ DWC_WRITE_REG32(&dev_if->
+ dev_global_regs->diepeachintmsk[ep->
+ num],
+ diepmsk.d32);
} else {
doepmsk_data_t doepmsk = {.d32 = 0 };
if (ep->type == DWC_OTG_EP_TYPE_ISOC)
doepmsk.b.outtknepdis = 1;
-/*
-
+ /*
if (core_if->dma_desc_enable) {
doepmsk.b.bna = 1;
}
-*/
-/*
doepmsk.b.babble = 1;
doepmsk.b.nyet = 1;
doepmsk.b.nak = 1;
-*/
- DWC_WRITE_REG32(&dev_if->dev_global_regs->
- doepeachintmsk[ep->num], doepmsk.d32);
+ */
+
+ DWC_WRITE_REG32(&dev_if->
+ dev_global_regs->doepeachintmsk[ep->
+ num],
+ doepmsk.d32);
}
DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
0, daintmsk.d32);
if (ep->is_in) {
diepmsk_data_t diepmsk = {.d32 = 0 };
diepmsk.b.nak = 1;
- DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->
+ diepmsk, 0, diepmsk.d32);
} else {
doepmsk_data_t doepmsk = {.d32 = 0 };
doepmsk.b.outtknepdis = 1;
- DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->
+ doepmsk, 0, doepmsk.d32);
}
}
DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to deactivate.
*/
-void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl = {.d32 = 0 };
volatile uint32_t *addr;
depctl.b.usbactep = 0;
- /* Update nextep_seq array and EPMSCNT in DCFG */
- if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
+ /* Update nextep_seq array and EPMSCNT in DCFG
+ * NP EP IN */
+ if (!(depctl.b.eptype & 1) && ep->is_in == 1) {
for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
if (core_if->nextep_seq[i] == ep->num)
break;
DWC_DEBUGPL(DBG_PCDV,
"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
__func__, core_if->first_in_nextep_seq);
- for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++)
DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
- }
}
-
+
if (ep->is_in == 1)
depctl.b.txfnum = 0;
diepint_data_t diepint = {.d32 = 0 };
depctl.b.snak = 1;
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
- diepctl, depctl.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->
+ in_ep_regs[ep->num]->diepctl,
+ depctl.d32);
do {
dwc_udelay(10);
diepint.d32 =
- DWC_READ_REG32(&core_if->
- dev_if->in_ep_regs[ep->num]->
- diepint);
+ DWC_READ_REG32(&core_if->dev_if->
+ in_ep_regs[ep->
+ num]->diepint);
} while (!diepint.b.inepnakeff);
diepint.b.inepnakeff = 1;
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
- diepint, diepint.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->
+ in_ep_regs[ep->num]->diepint,
+ diepint.d32);
depctl.d32 = 0;
depctl.b.epdis = 1;
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
- diepctl, depctl.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->
+ in_ep_regs[ep->num]->diepctl,
+ depctl.d32);
do {
dwc_udelay(10);
diepint.d32 =
- DWC_READ_REG32(&core_if->
- dev_if->in_ep_regs[ep->num]->
- diepint);
+ DWC_READ_REG32(&core_if->dev_if->
+ in_ep_regs[ep->
+ num]->diepint);
} while (!diepint.b.epdisabled);
diepint.b.epdisabled = 1;
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
- diepint, diepint.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->
+ in_ep_regs[ep->num]->diepint,
+ diepint.d32);
} else {
- dctl_data_t dctl = {.d32 = 0};
- gintmsk_data_t gintsts = {.d32 = 0};
- doepint_data_t doepint = {.d32 = 0};
+ dctl_data_t dctl = {.d32 = 0 };
+ gintmsk_data_t gintsts = {.d32 = 0 };
+ doepint_data_t doepint = {.d32 = 0 };
dctl.b.sgoutnak = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
- dctl, 0, dctl.d32);
+ DWC_MODIFY_REG32(&core_if->dev_if->
+ dev_global_regs->dctl, 0, dctl.d32);
do {
dwc_udelay(10);
- gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
- } while (!gintsts.b.goutnakeff);
+ gintsts.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->
+ gintsts);
+ } while (!gintsts.b.goutnakeff);
gintsts.d32 = 0;
gintsts.b.goutnakeff = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,
+ gintsts.d32);
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
- DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
- do
- {
+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
+ doepctl, depctl.d32);
+ do {
dwc_udelay(10);
- doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[ep->num]->doepint);
- } while (!doepint.b.epdisabled);
+ doepint.d32 =
+ DWC_READ_REG32(&core_if->
+ dev_if->out_ep_regs[ep->
+ num]->
+ doepint);
+ } while (!doepint.b.epdisabled);
doepint.b.epdisabled = 1;
- DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
+ doepint, doepint.d32);
dctl.d32 = 0;
dctl.b.cgoutnak = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
- }
+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+ dctl, 0, dctl.d32);
+ }
}
/* Disable the Interrupt for this EP */
daintmsk.d32, 0);
if (ep->is_in == 1) {
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
- diepeachintmsk[ep->num], 0);
+ DWC_WRITE_REG32(&core_if->dev_if->
+ dev_global_regs->diepeachintmsk[ep->
+ num],
+ 0);
} else {
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
- doepeachintmsk[ep->num], 0);
+ DWC_WRITE_REG32(&core_if->dev_if->
+ dev_global_regs->doepeachintmsk[ep->
+ num],
+ 0);
}
} else {
DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to start the transfer on.
*/
-static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
dwc_otg_dev_dma_desc_t *dma_desc;
uint32_t offset;
if (ep->is_in) {
dma_desc->status.b.sp =
(xfer_est %
- ep->maxpacket) ? 1 : ((ep->
- sent_zlp) ? 1 : 0);
+ ep->
+ maxpacket) ? 1 : ((ep->sent_zlp) ? 1 : 0);
dma_desc->status.b.bytes = xfer_est;
} else {
if (maxxfer_local == ep->maxpacket)
dma_desc->status.b.bytes = xfer_est;
- else
+ else
dma_desc->status.b.bytes =
- xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
+ xfer_est +
+ ((4 - (xfer_est & 0x3)) & 0x3);
}
dma_desc->buf = ep->dma_addr + offset;
}
/**
- * This function is called when to write ISOC data into appropriate dedicated
+ * This function is called when to write ISOC data into appropriate dedicated
* periodic FIFO.
*/
-static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
+static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t *core_if,
+ dwc_ep_t *dwc_ep)
{
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
dwc_otg_dev_in_ep_regs_t *ep_regs;
len = dwc_ep->xfer_len - dwc_ep->xfer_count;
- if (len > dwc_ep->maxpacket) {
+ if (len > dwc_ep->maxpacket)
len = dwc_ep->maxpacket;
- }
dwords = (len + 3) / 4;
dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
len = dwc_ep->xfer_len - dwc_ep->xfer_count;
- if (len > dwc_ep->maxpacket) {
+ if (len > dwc_ep->maxpacket)
len = dwc_ep->maxpacket;
- }
dwords = (len + 3) / 4;
txstatus.d32 =
* @param ep The EP to start the transfer on.
*/
-void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl;
deptsiz_data_t deptsiz;
deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
- ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
- ep->maxxfer : (ep->total_len - ep->xfer_len);
- else
- ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
- MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-
+ ep->xfer_len +=
+ (ep->maxxfer <
+ (ep->total_len -
+ ep->xfer_len)) ? ep->maxxfer : (ep->total_len -
+ ep->xfer_len);
+ else
+ ep->xfer_len +=
+ (MAX_PKT_CNT * ep->maxpacket <
+ (ep->total_len -
+ ep->xfer_len)) ? MAX_PKT_CNT *
+ ep->maxpacket : (ep->total_len - ep->xfer_len);
/* Zero Length Packet? */
if ((ep->xfer_len - ep->xfer_count) == 0) {
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
+ * exist ? 1 : 0)
*/
deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
deptsiz.b.pktcnt =
ep->maxpacket) / ep->maxpacket;
if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
deptsiz.b.pktcnt = MAX_PKT_CNT;
- deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
- }
- if (ep->type == DWC_OTG_EP_TYPE_ISOC)
+ deptsiz.b.xfersize =
+ deptsiz.b.pktcnt * ep->maxpacket;
+ }
+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
deptsiz.b.mc = deptsiz.b.pktcnt;
}
(uint32_t) ep->dma_addr);
} else {
#ifdef DWC_UTE_CFI
- /* The descriptor chain should be already initialized by now */
+ /* The descriptor chain should be
+ * already initialized by now */
if (ep->buff_mode != BM_STANDARD) {
DWC_WRITE_REG32(&in_regs->diepdma,
ep->descs_dma_addr);
if (core_if->en_multiple_tx_fifo == 0) {
intr_mask.b.nptxfempty = 1;
DWC_MODIFY_REG32
- (&core_if->core_global_regs->gintmsk,
- intr_mask.d32, intr_mask.d32);
+ (&core_if->core_global_regs->
+ gintmsk, intr_mask.d32,
+ intr_mask.d32);
} else {
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0) {
uint32_t fifoemptymsk = 0;
fifoemptymsk = 1 << ep->num;
DWC_MODIFY_REG32
- (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
- 0, fifoemptymsk);
+ (&core_if->dev_if->
+ dev_global_regs->
+ dtknqr4_fifoemptymsk, 0,
+ fifoemptymsk);
}
}
write_isoc_tx_fifo(core_if, ep);
}
}
- if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+ if (!core_if->core_params->en_multiple_tx_fifo
+ && core_if->dma_enable)
depctl.b.nextep = core_if->nextep_seq[ep->num];
if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
dsts_data_t dsts = {.d32 = 0 };
if (ep->bInterval == 1) {
dsts.d32 =
- DWC_READ_REG32(&core_if->dev_if->
- dev_global_regs->dsts);
+ DWC_READ_REG32(&core_if->
+ dev_if->dev_global_regs->
+ dsts);
ep->frame_num = dsts.b.soffn + ep->bInterval;
if (ep->frame_num > 0x3FFF) {
ep->frm_overrun = 1;
ep->frame_num &= 0x3FFF;
} else
ep->frm_overrun = 0;
- if (ep->frame_num & 0x1) {
+ if (ep->frame_num & 0x1)
depctl.b.setd1pid = 1;
- } else {
+ else
depctl.b.setd0pid = 1;
- }
}
}
/* EP enable, IN data in FIFO */
depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
- if (!core_if->dma_desc_enable) {
+ if (!core_if->dma_desc_enable) {
if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
- ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
- ep->maxxfer : (ep->total_len - ep->xfer_len);
- else
- ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
- - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
+ ep->xfer_len +=
+ (ep->maxxfer <
+ (ep->total_len -
+ ep->xfer_len)) ? ep->maxxfer : (ep->
+ total_len
+ -
+ ep->
+ xfer_len);
+ else
+ ep->xfer_len +=
+ (MAX_PKT_CNT * ep->maxpacket <
+ (ep->total_len -
+ ep->xfer_len)) ? MAX_PKT_CNT *
+ ep->maxpacket : (ep->total_len -
+ ep->xfer_len);
}
/* Program the transfer size and packet count as follows:
*
- * pktcnt = N
- * xfersize = N * maxpacket
+ * pktcnt = N
+ * xfersize = N * maxpacket
*/
if ((ep->xfer_len - ep->xfer_count) == 0) {
/* Zero Length Packet */
deptsiz.b.pktcnt =
(ep->xfer_len - ep->xfer_count +
(ep->maxpacket - 1)) / ep->maxpacket;
- if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
+ if (deptsiz.b.pktcnt > MAX_PKT_CNT)
deptsiz.b.pktcnt = MAX_PKT_CNT;
- }
if (!core_if->dma_desc_enable) {
ep->xfer_len =
- deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
+ deptsiz.b.pktcnt * ep->maxpacket +
+ ep->xfer_count;
}
deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
}
(uint32_t) ep->dma_addr);
} else {
#ifdef DWC_UTE_CFI
- /* The descriptor chain should be already initialized by now */
+ /* The descriptor chain should be
+ * already initialized by now */
if (ep->buff_mode != BM_STANDARD) {
DWC_WRITE_REG32(&out_regs->doepdma,
ep->descs_dma_addr);
} else {
#endif
- /** This is used for interrupt out transfers*/
+ /* This is used for
+ * interrupt out transfers*/
if (!ep->xfer_len)
ep->xfer_len = ep->total_len;
init_dma_desc_chain(core_if, ep);
if (core_if->core_params->dev_out_nak) {
- if (ep->type == DWC_OTG_EP_TYPE_BULK) {
- deptsiz.b.pktcnt = (ep->total_len +
- (ep->maxpacket - 1)) / ep->maxpacket;
- deptsiz.b.xfersize = ep->total_len;
+ if (ep->type ==
+ DWC_OTG_EP_TYPE_BULK) {
+ deptsiz.b.pktcnt =
+ (ep->total_len +
+ (ep->maxpacket -
+ 1)) /
+ ep->maxpacket;
+ deptsiz.b.xfersize =
+ ep->total_len;
/* Remember initial value of doeptsiz */
- core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
- DWC_WRITE_REG32(&out_regs->doeptsiz,
- deptsiz.d32);
+ core_if->
+ start_doeptsiz_val
+ [ep->num] =
+ deptsiz.d32;
+ DWC_WRITE_REG32
+ (&out_regs->
+ doeptsiz,
+ deptsiz.d32);
}
}
/** DOEPDMAn Register write */
dsts_data_t dsts = {.d32 = 0 };
if (ep->bInterval == 1) {
dsts.d32 =
- DWC_READ_REG32(&core_if->dev_if->
- dev_global_regs->dsts);
+ DWC_READ_REG32(&core_if->
+ dev_if->dev_global_regs->
+ dsts);
ep->frame_num = dsts.b.soffn + ep->bInterval;
if (ep->frame_num > 0x3FFF) {
ep->frm_overrun = 1;
} else
ep->frm_overrun = 0;
- if (ep->frame_num & 0x1) {
+ if (ep->frame_num & 0x1)
depctl.b.setd1pid = 1;
- } else {
+ else
depctl.b.setd0pid = 1;
- }
}
}
DWC_READ_REG32(&out_regs->doepctl),
DWC_READ_REG32(&out_regs->doeptsiz));
DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
- DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
- daintmsk),
- DWC_READ_REG32(&core_if->core_global_regs->
- gintmsk));
-
- /* Timer is scheduling only for out bulk transfers for
- * "Device DDMA OUT NAK Enhancement" feature to inform user
- * about received data payload in case of timeout
+ DWC_READ_REG32(&core_if->dev_if->
+ dev_global_regs->daintmsk),
+ DWC_READ_REG32(&core_if->
+ core_global_regs->gintmsk));
+
+ /* Timer is scheduling only for out bulk transfers for
+ * "Device DDMA OUT NAK Enhancement" feature to inform user
+ * about received data payload in case of timeout
*/
if (core_if->core_params->dev_out_nak) {
if (ep->type == DWC_OTG_EP_TYPE_BULK) {
- core_if->ep_xfer_info[ep->num].core_if = core_if;
+ core_if->ep_xfer_info[ep->num].core_if =
+ core_if;
core_if->ep_xfer_info[ep->num].ep = ep;
core_if->ep_xfer_info[ep->num].state = 1;
/* Start a timer for this transfer. */
- DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
+ DWC_TIMER_SCHEDULE(core_if->
+ ep_xfer_timer[ep->num],
+ 10000);
}
}
}
* @param ep The EP to start the transfer on.
*
*/
-void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl;
*/
if (core_if->en_multiple_tx_fifo == 0) {
intr_mask.b.nptxfempty = 1;
- DWC_MODIFY_REG32(&core_if->
- core_global_regs->gintmsk,
- intr_mask.d32, intr_mask.d32);
+ DWC_MODIFY_REG32(&core_if->core_global_regs->
+ gintmsk, intr_mask.d32,
+ intr_mask.d32);
} else {
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0) {
uint32_t fifoemptymsk = 0;
fifoemptymsk = 1 << ep->num;
- DWC_MODIFY_REG32(&core_if->
- dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+ DWC_MODIFY_REG32(&core_if->dev_if->
+ dev_global_regs->
+ dtknqr4_fifoemptymsk,
0, fifoemptymsk);
}
}
}
- if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+ if (!core_if->core_params->en_multiple_tx_fifo
+ && core_if->dma_enable)
depctl.b.nextep = core_if->nextep_seq[ep->num];
/* EP enable, IN data in FIFO */
depctl.b.cnak = 1;
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP0 data.
*/
-void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl;
deptsiz0_data_t deptsiz;
gtxstatus.d32 =
DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
- /* If dedicated FIFO every time flush fifo before enable ep*/
- if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
+ /* If dedicated FIFO every time flush fifo before enable ep */
+ if (core_if->en_multiple_tx_fifo
+ && core_if->snpsid >= OTG_CORE_REV_3_00a)
dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
if (core_if->en_multiple_tx_fifo == 0
- && gtxstatus.b.nptxqspcavail == 0
- && !core_if->dma_enable) {
+ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
#ifdef DEBUG
deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
+ * exist ? 1 : 0)
*/
if (ep->xfer_len > ep->maxpacket) {
ep->xfer_len = ep->maxpacket;
/** DIEPDMA0 Register write */
DWC_WRITE_REG32(&in_regs->diepdma,
- core_if->
- dev_if->dma_in_desc_addr);
+ core_if->dev_if->
+ dma_in_desc_addr);
}
} else {
DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
}
- if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+ if (!core_if->core_params->en_multiple_tx_fifo
+ && core_if->dma_enable)
depctl.b.nextep = core_if->nextep_seq[ep->num];
/* EP enable, IN data in FIFO */
depctl.b.cnak = 1;
if (!core_if->dma_enable) {
if (core_if->en_multiple_tx_fifo == 0) {
intr_mask.b.nptxfempty = 1;
- DWC_MODIFY_REG32(&core_if->
- core_global_regs->gintmsk,
- intr_mask.d32, intr_mask.d32);
+ DWC_MODIFY_REG32(&core_if->core_global_regs->
+ gintmsk, intr_mask.d32,
+ intr_mask.d32);
} else {
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0) {
uint32_t fifoemptymsk = 0;
fifoemptymsk |= 1 << ep->num;
- DWC_MODIFY_REG32(&core_if->
- dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+ DWC_MODIFY_REG32(&core_if->dev_if->
+ dev_global_regs->
+ dtknqr4_fifoemptymsk,
0, fifoemptymsk);
}
}
deptsiz.b.xfersize = ep->maxpacket;
deptsiz.b.pktcnt = 1;
if (core_if->snpsid >= OTG_CORE_REV_3_00a)
- deptsiz.b.supcnt = 3;
+ deptsiz.b.supcnt = 1;
DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
/** DOEPDMA0 Register write */
DWC_WRITE_REG32(&out_regs->doepdma,
- core_if->dev_if->
- dma_out_desc_addr);
+ core_if->
+ dev_if->dma_out_desc_addr);
}
} else {
DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP0 data.
*/
-void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl;
deptsiz0_data_t deptsiz;
deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
/* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
*/
if (core_if->dma_desc_enable == 0) {
ep->maxpacket ? ep->maxpacket : (ep->total_len -
ep->xfer_count);
deptsiz.b.pktcnt = 1;
- if (core_if->dma_enable == 0) {
+ if (core_if->dma_enable == 0)
ep->xfer_len += deptsiz.b.xfersize;
- } else {
+ else
ep->xfer_len = deptsiz.b.xfersize;
- }
DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
} else {
ep->xfer_len =
DWC_WRITE_REG32(&(in_regs->diepdma),
(uint32_t) ep->dma_addr);
}
- if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+ if (!core_if->core_params->en_multiple_tx_fifo
+ && core_if->dma_enable)
depctl.b.nextep = core_if->nextep_seq[ep->num];
/* EP enable, IN data in FIFO */
depctl.b.cnak = 1;
if (core_if->en_multiple_tx_fifo == 0) {
/* First clear it from GINTSTS */
intr_mask.b.nptxfempty = 1;
- DWC_MODIFY_REG32(&core_if->
- core_global_regs->gintmsk,
- intr_mask.d32, intr_mask.d32);
+ DWC_MODIFY_REG32(&core_if->core_global_regs->
+ gintmsk, intr_mask.d32,
+ intr_mask.d32);
} else {
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0) {
uint32_t fifoemptymsk = 0;
fifoemptymsk |= 1 << ep->num;
- DWC_MODIFY_REG32(&core_if->
- dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+ DWC_MODIFY_REG32(&core_if->dev_if->
+ dev_global_regs->
+ dtknqr4_fifoemptymsk,
0, fifoemptymsk);
}
}
deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
/* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
*/
deptsiz.b.xfersize = ep->maxpacket;
deptsiz.b.pktcnt = 1;
}
#ifdef DEBUG
-void dump_msg(const u8 * buf, unsigned int length)
+void dump_msg(const u8 *buf, unsigned int length)
{
unsigned int start, num, i;
char line[52], *p;
}
}
#else
-static inline void dump_msg(const u8 * buf, unsigned int length)
+static inline void dump_msg(const u8 *buf, unsigned int length)
{
}
#endif
* @param ep The EP to write packet for.
* @param dma Indicates if DMA is being used.
*/
-void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
+void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep,
int dma)
{
/**
}
/* Find the byte length of the packet either short packet or MPS */
- if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
+ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket)
byte_count = ep->xfer_len - ep->xfer_count;
- } else {
+ else
byte_count = ep->maxpacket;
- }
/* Find the DWORD length, padded by extra bytes as neccessary if MPS
* is not a multiple of DWORD */
fifo, data_buff, *data_buff, byte_count);
if (!dma) {
- for (i = 0; i < dword_count; i++, data_buff++) {
+ for (i = 0; i < dword_count; i++, data_buff++)
DWC_WRITE_REG32(fifo, *data_buff);
- }
}
ep->xfer_count += byte_count;
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to set the stall on.
*/
-void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl;
volatile uint32_t *depctl_addr;
depctl.d32 = DWC_READ_REG32(depctl_addr);
/* set the disable and stall bits */
- if (depctl.b.epena) {
+ if (depctl.b.epena)
depctl.b.epdis = 1;
- }
depctl.b.stall = 1;
DWC_WRITE_REG32(depctl_addr, depctl.d32);
} else {
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to clear stall from.
*/
-void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
depctl_data_t depctl;
volatile uint32_t *depctl_addr;
DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
(ep->is_in ? "IN" : "OUT"));
- if (ep->is_in == 1) {
+ if (ep->is_in == 1)
depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
- } else {
+ else
depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
- }
depctl.d32 = DWC_READ_REG32(depctl_addr);
* @param dest Destination buffer for the packet.
* @param bytes Number of bytes to copy to the destination.
*/
-void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
- uint8_t * dest, uint16_t bytes)
+void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
+ uint8_t *dest, uint16_t bytes)
{
int i;
int word_count = (bytes + 3) / 4;
DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
core_if, dest, bytes);
- for (i = 0; i < word_count; i++, data_buff++) {
+ for (i = 0; i < word_count; i++, data_buff++)
*data_buff = DWC_READ_REG32(fifo);
- }
return;
}
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
{
int i;
volatile uint32_t *addr;
for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
addr =
- &core_if->dev_if->
- dev_global_regs->diepeachintmsk[i];
+ &core_if->dev_if->dev_global_regs->
+ diepeachintmsk[i];
DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
i, (unsigned long)addr,
DWC_READ_REG32(addr));
for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
addr =
- &core_if->dev_if->
- dev_global_regs->doepeachintmsk[i];
+ &core_if->dev_if->dev_global_regs->
+ doepeachintmsk[i];
DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
i, (unsigned long)addr,
DWC_READ_REG32(addr));
}
for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
- if(hwcfg1 & (2<<(i<<1))){
+ if (hwcfg1 & (2 << (i << 1))) {
DWC_PRINTF("Device IN EP %d Registers\n", i);
addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
(unsigned long)addr, DWC_READ_REG32(addr));
addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
- (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
+ (unsigned long)addr,
+ 0 /*DWC_READ_REG32(addr) */);
}
}
for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
- if(hwcfg1 & (1<<(i<<1))){
+ if (hwcfg1 & (1 << (i << 1))) {
DWC_PRINTF("Device OUT EP %d Registers\n", i);
addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
(unsigned long)addr, DWC_READ_REG32(addr));
- if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
- addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
+ /* Don't access this register in SLAVE mode */
+ if (core_if->dma_enable) {
+ addr =
+ &core_if->dev_if->out_ep_regs[i]->doepdmab;
DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
- (unsigned long)addr, DWC_READ_REG32(addr));
+ (unsigned long)addr,
+ DWC_READ_REG32(addr));
}
}
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
+void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
{
volatile uint8_t *addr, *start_addr, *end_addr;
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
+void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
{
int i;
volatile uint32_t *addr;
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
+void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
{
int i, ep_num;
volatile uint32_t *addr;
addr = &core_if->core_global_regs->gdfifocfg;
DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
DWC_READ_REG32(addr));
- addr = &core_if->core_global_regs->adpctl;
- DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
- dwc_otg_adp_read_reg(core_if));
addr = &core_if->core_global_regs->hptxfsiz;
DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
DWC_READ_REG32(addr));
* @param core_if Programming view of DWC_otg controller.
* @param num Tx FIFO to flush.
*/
-void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if, const int num)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
volatile grstctl_t greset = {.d32 = 0 };
*
* @param core_if Programming view of DWC_otg controller.
*/
-void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
volatile grstctl_t greset = {.d32 = 0 };
* Do core a soft reset of the core. Be careful with this because it
* resets all the internal state machines of the core.
*/
-void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
+void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
{
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
volatile grstctl_t greset = {.d32 = 0 };
+ volatile gusbcfg_data_t usbcfg = {.d32 = 0 };
int count = 0;
DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
greset.d32);
return;
}
- }
- while (greset.b.ahbidle == 0);
+ } while (greset.b.ahbidle == 0);
/* Core Soft Reset */
count = 0;
greset.b.csftrst = 1;
DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
+
do {
greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
if (++count > 10000) {
break;
}
dwc_udelay(1);
+ } while (greset.b.csftrst == 1);
+
+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+ if (core_if->usb_mode == USB_MODE_FORCE_HOST) {
+ usbcfg.b.force_host_mode = 1;
+ usbcfg.b.force_dev_mode = 0;
+ } else if (core_if->usb_mode == USB_MODE_FORCE_DEVICE) {
+ usbcfg.b.force_host_mode = 0;
+ usbcfg.b.force_dev_mode = 1;
+ } else {
+ usbcfg.b.force_host_mode = 0;
+ usbcfg.b.force_dev_mode = 0;
}
- while (greset.b.csftrst == 1);
+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
/* Wait for 3 PHY Clocks */
dwc_mdelay(100);
}
-uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
}
-uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
}
* @param cb the HCD callback structure.
* @param p pointer to be passed to callback function (usb_hcd*).
*/
-void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
- dwc_otg_cil_callbacks_t * cb, void *p)
+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
+ dwc_otg_cil_callbacks_t *cb, void *p)
{
core_if->hcd_cb = cb;
- //cb->p = p;
+ /* cb->p = p; */
core_if->hcd_cb_p = p;
}
* @param cb the PCD callback structure.
* @param p pointer to be passed to callback function (pcd*).
*/
-void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
- dwc_otg_cil_callbacks_t * cb, void *p)
+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
+ dwc_otg_cil_callbacks_t *cb, void *p)
{
core_if->pcd_cb = cb;
cb->p = p;
* @param ep The EP to start the transfer on.
*
*/
-void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
dwc_otg_dev_in_ep_regs_t *ep_regs;
dtxfsts_data_t txstatus = {.d32 = 0 };
dwords = (len + 3) / 4;
txstatus.d32 =
- DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
- dtxfsts);
+ DWC_READ_REG32(&core_if->dev_if->
+ in_ep_regs[ep->num]->dtxfsts);
DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
txstatus.d32);
}
* @param ep The EP to start the transfer on.
*
*/
-void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
- dwc_ep_t * ep)
+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if,
+ dwc_ep_t *ep)
{
deptsiz_data_t deptsiz = {.d32 = 0 };
depctl_data_t depctl = {.d32 = 0 };
dsts_data_t dsts = {.d32 = 0 };
volatile uint32_t *addr;
- if (ep->is_in) {
+ if (ep->is_in)
addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
- } else {
+ else
addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
- }
ep->xfer_len = ep->data_per_frame;
ep->xfer_count = 0;
if (ep->is_in) {
/* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
*/
deptsiz.b.xfersize = ep->xfer_len;
deptsiz.b.pktcnt =
/* Write the DMA register */
if (core_if->dma_enable) {
DWC_WRITE_REG32(&
- (core_if->dev_if->in_ep_regs[ep->num]->
- diepdma), (uint32_t) ep->dma_addr);
+ (core_if->dev_if->
+ in_ep_regs[ep->num]->diepdma),
+ (uint32_t) ep->dma_addr);
}
} else {
deptsiz.b.pktcnt =
(ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
- DWC_WRITE_REG32(&core_if->dev_if->
- out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
+ doeptsiz, deptsiz.d32);
if (core_if->dma_enable) {
DWC_WRITE_REG32(&
- (core_if->dev_if->
- out_ep_regs[ep->num]->doepdma),
- (uint32_t) ep->dma_addr);
+ (core_if->dev_if->out_ep_regs[ep->num]->
+ doepdma), (uint32_t) ep->dma_addr);
}
}
DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
ep->next_frame = dsts.b.soffn + ep->bInterval;
- if (ep->next_frame & 0x1) {
+ if (ep->next_frame & 0x1)
depctl.b.setd1pid = 1;
- } else {
+ else
depctl.b.setd0pid = 1;
- }
} else {
ep->next_frame += ep->bInterval;
- if (ep->next_frame & 0x1) {
+ if (ep->next_frame & 0x1)
depctl.b.setd1pid = 1;
- } else {
+ else
depctl.b.setd0pid = 1;
- }
}
depctl.b.epena = 1;
depctl.b.cnak = 1;
}
#endif /* DWC_EN_ISOC */
-static void dwc_otg_set_uninitialized(int32_t * p, int size)
+static void dwc_otg_set_uninitialized(int32_t *p, int size)
{
int i;
for (i = 0; i < size; i++) {
return val != -1;
}
-static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
+static int dwc_otg_setup_params(dwc_otg_core_if_t *core_if)
{
- int i;
gintsts_data_t gintsts;
gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
- if (!core_if->core_params) {
+ if (!core_if->core_params)
return -DWC_E_NO_MEMORY;
- }
dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
sizeof(*core_if->core_params) /
sizeof(int32_t));
dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
dwc_otg_set_param_en_multiple_tx_fifo(core_if,
dwc_param_en_multiple_tx_fifo_default);
-
+
+ /* do not set dev_perio_tx_fifo_size and dev_tx_fifo_size here
+ * set validate parameter values in "set_parameters" later.
+ */
+#if 0
if (gintsts.b.curmode) {
/* Force device mode to get power-on values of device FIFOs */
gusbcfg_data_t gusbcfg = {.d32 = 0 };
- gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+ gusbcfg.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
gusbcfg.b.force_dev_mode = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
+ gusbcfg.d32);
dwc_mdelay(100);
for (i = 0; i < 15; i++) {
- dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
- dwc_param_dev_perio_tx_fifo_size_default, i);
+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+ dwc_param_dev_perio_tx_fifo_size_default,
+ i);
}
for (i = 0; i < 15; i++) {
dwc_otg_set_param_dev_tx_fifo_size(core_if,
- dwc_param_dev_tx_fifo_size_default, i);
+ dwc_param_dev_tx_fifo_size_default,
+ i);
}
- gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+ gusbcfg.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
gusbcfg.b.force_dev_mode = 0;
- DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
+ gusbcfg.d32);
dwc_mdelay(100);
} else {
for (i = 0; i < 15; i++) {
dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
- dwc_param_dev_perio_tx_fifo_size_default, i);
+ dwc_param_dev_perio_tx_fifo_size_default,
+ i);
}
for (i = 0; i < 15; i++) {
dwc_otg_set_param_dev_tx_fifo_size(core_if,
- dwc_param_dev_tx_fifo_size_default, i);
+ dwc_param_dev_tx_fifo_size_default,
+ i);
}
}
-
+#endif
dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
-
+
dwc_otg_set_param_besl_enable(core_if, dwc_param_besl_enable_default);
- dwc_otg_set_param_baseline_besl(core_if, dwc_param_baseline_besl_default);
+ dwc_otg_set_param_baseline_besl(core_if,
+ dwc_param_baseline_besl_default);
dwc_otg_set_param_deep_besl(core_if, dwc_param_deep_besl_default);
-
+
dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
dwc_otg_set_param_tx_thr_length(core_if,
dwc_param_tx_thr_length_default);
return 0;
}
-uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t *core_if)
{
return core_if->dma_enable;
}
((_param_) > (_high_)))
/* Parameter access functions */
-int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t *core_if, int32_t val)
{
int valid;
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->otg_cap;
}
-int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_opt(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
DWC_WARN("Wrong value for opt parameter\n");
return 0;
}
-int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->opt;
}
-int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dma_enable;
}
-int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dma_desc_enable;
}
-int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *core_if,
int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return 0;
}
-int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
- core_if)
+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
+ *core_if)
{
return core_if->core_params->host_support_fs_ls_low_power;
}
-int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->enable_dynamic_fifo;
}
-int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
return retval;
}
-int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->data_fifo_size;
}
-int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
}
if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
- if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
- DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
+ if (dwc_otg_param_initialized
+ (core_if->core_params->dev_rx_fifo_size)) {
+ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n",
+ val);
}
val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
retval = -DWC_E_INVALID;
return retval;
}
-int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dev_rx_fifo_size;
}
-int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dev_nperio_tx_fifo_size;
}
-int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
}
-int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->host_rx_fifo_size;
}
-int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->host_nperio_tx_fifo_size;
}
-int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->host_perio_tx_fifo_size;
}
-int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->max_transfer_size;
}
-int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->max_packet_count;
}
-int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->host_channels;
}
-int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dev_endpoints;
}
-int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 0;
return retval;
}
-int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->phy_type;
}
-int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_speed(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->speed;
}
-int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->host_ls_low_power_phy_clk;
}
-int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
DWC_WARN("Wrong value for phy_ulpi_ddr\n");
return 0;
}
-int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->phy_ulpi_ddr;
}
-int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t *core_if,
int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return 0;
}
-int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->phy_ulpi_ext_vbus;
}
-int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
DWC_WARN("Wrong valaue for phy_utmi_width\n");
return 0;
}
-int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->phy_utmi_width;
}
-int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
return 0;
}
-int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->ulpi_fs_ls;
}
-int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
DWC_WARN("Wrong valaue for ts_dline\n");
return 0;
}
-int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->ts_dline;
}
-int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->i2c_enable;
}
-int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
int32_t val, int fifo_num)
{
int retval = 0;
gintsts_data_t gintsts;
gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
- if (core_if->hwcfg4.b.ded_fifo_en == 0){
+ if (core_if->hwcfg4.b.ded_fifo_en == 0) {
if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
return -DWC_E_INVALID;
}
- if (val > (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
- printk("%d ",DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16);
- printk("val = %d fifo_num = %d\n",val,fifo_num);
+ if (val >
+ (DWC_READ_REG32
+ (&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
+ printk("%d ",
+ DWC_READ_REG32(&core_if->core_global_regs->
+ dtxfsiz[fifo_num]) >> 16);
+ printk("val = %d fifo_num = %d\n", val, fifo_num);
DWC_WARN("Value is larger then power-on FIFO size\n");
if (dwc_otg_param_initialized
- (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
+ (core_if->core_params->
+ dev_perio_tx_fifo_size[fifo_num])) {
DWC_ERROR
- ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
- val, fifo_num);
+ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
+ val, fifo_num);
}
- val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16);
+ val =
+ (DWC_READ_REG32
+ (&core_if->core_global_regs->
+ dtxfsiz[fifo_num]) >> 16);
retval = -DWC_E_INVALID;
}
return retval;
}
-int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
int fifo_num)
{
return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
}
-int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t *core_if,
int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->en_multiple_tx_fifo;
}
-int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t *core_if, int32_t val,
int fifo_num)
{
int retval = 0;
fifosize_data_t txfifosize;
- txfifosize.d32 = DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]);
+ txfifosize.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]);
if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
DWC_WARN("Wrong value for dev_tx_fifo_size\n");
return retval;
}
-int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t *core_if,
int fifo_num)
{
return core_if->core_params->dev_tx_fifo_size[fifo_num];
}
-int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->thr_ctl;
}
-int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->lpm_enable;
}
-int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
}
core_if->core_params->besl_enable = val;
-
- if(val)
- {
- retval += dwc_otg_set_param_lpm_enable(core_if,val);
+
+ if (val) {
+ retval += dwc_otg_set_param_lpm_enable(core_if, val);
}
-
+
return retval;
}
-int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->besl_enable;
}
-int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
-
+
if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
DWC_WARN("Wrong value for baseline_besl\n");
DWC_WARN("baseline_besl must be 0-15\n");
return retval;
}
-int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->baseline_besl;
}
-int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->deep_besl;
}
-int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
DWC_WARN("Wrong valaue for tx_thr_length\n");
return 0;
}
-int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->tx_thr_length;
}
-int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
DWC_WARN("Wrong valaue for rx_thr_length\n");
return 0;
}
-int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->rx_thr_length;
}
-int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t *core_if, int32_t val)
{
if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
DWC_OTG_PARAM_TEST(val, 4, 4) &&
return 0;
}
-int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dma_burst_size;
}
-int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->pti_enable;
}
-int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->mpi_enable;
}
-int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->adp_supp_enable;
}
-int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
return retval;
}
-int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->ic_usb_cap;
}
-int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 1;
return retval;
}
-int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->ahb_thr_ratio;
}
-int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_power_down(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 1;
return retval;
}
-int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->power_down;
}
-int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 1;
return retval;
}
-int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->reload_ctl;
}
-int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 1;
valid = 0;
}
if (valid == 0) {
- if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
+ if (dwc_otg_param_initialized
+ (core_if->core_params->dev_out_nak)) {
DWC_ERROR("%d invalid for parameter dev_out_nak."
"Check HW configuration.\n", val);
}
return retval;
}
-int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->dev_out_nak;
}
-int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 1;
valid = 0;
}
if (valid == 0) {
- if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
+ if (dwc_otg_param_initialized
+ (core_if->core_params->cont_on_bna)) {
DWC_ERROR("%d invalid for parameter cont_on_bna."
- "Check HW configuration.\n", val);
+ "Check HW configuration.\n", val);
}
retval = -DWC_E_INVALID;
val = 0;
return retval;
}
-int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->cont_on_bna;
}
-int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
int valid = 1;
return retval;
}
-int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->ahb_single;
}
-int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
+int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t *core_if, int32_t val)
{
int retval = 0;
return retval;
}
-int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
+int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t *core_if)
{
return core_if->core_params->otg_ver;
}
-uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t *core_if)
{
gotgctl_data_t otgctl;
otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
return otgctl.b.hstnegscs;
}
-uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t *core_if)
{
gotgctl_data_t otgctl;
otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
return otgctl.b.sesreqscs;
}
-void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_hnpreq(dwc_otg_core_if_t *core_if, uint32_t val)
{
- if(core_if->otg_ver == 0) {
+ if (core_if->otg_ver == 0) {
gotgctl_data_t otgctl;
- otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+ otgctl.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
otgctl.b.hnpreq = val;
- DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl,
+ otgctl.d32);
} else {
core_if->otg_sts = val;
}
}
-uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t *core_if)
{
return core_if->snpsid;
}
-uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t *core_if)
{
gintsts_data_t gintsts;
gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
return gintsts.b.curmode;
}
-uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t *core_if)
{
gusbcfg_data_t usbcfg;
usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
return usbcfg.b.hnpcap;
}
-void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t *core_if, uint32_t val)
{
gusbcfg_data_t usbcfg;
usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
}
-uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t *core_if)
{
gusbcfg_data_t usbcfg;
usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
return usbcfg.b.srpcap;
}
-void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_srpcapable(dwc_otg_core_if_t *core_if, uint32_t val)
{
gusbcfg_data_t usbcfg;
usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
}
-uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t *core_if)
{
dcfg_data_t dcfg;
dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
return dcfg.b.devspd;
}
-void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_devspeed(dwc_otg_core_if_t *core_if, uint32_t val)
{
dcfg_data_t dcfg;
dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
}
-uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t *core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
return hprt0.b.prtconnsts;
}
-uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t *core_if)
{
dsts_data_t dsts;
dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
return dsts.b.enumspd;
}
-uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t *core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
}
-uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t *core_if)
{
return core_if->hibernation_suspend;
}
-void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_prtpower(dwc_otg_core_if_t *core_if, uint32_t val)
{
hprt0_data_t hprt0;
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
}
-uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t *core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
}
-void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t *core_if, uint32_t val)
{
hprt0_data_t hprt0;
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
}
-uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t *core_if)
{
hfir_data_t hfir;
hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
}
-void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_fr_interval(dwc_otg_core_if_t *core_if, uint32_t val)
{
hfir_data_t hfir;
uint32_t fram_int;
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
}
-uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t *core_if)
{
hcfg_data_t hcfg;
hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
}
-void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t *core_if, uint32_t val)
{
hcfg_data_t hcfg;
hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
}
-void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_prtresume(dwc_otg_core_if_t *core_if, uint32_t val)
{
hprt0_data_t hprt0;
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
}
-uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t *core_if)
{
dctl_data_t dctl;
dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
return dctl.b.rmtwkupsig;
}
-uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t *core_if)
{
dctl_data_t dctl;
dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
return dctl.b.besl_reject;
}
-void dwc_otg_set_beslreject(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_beslreject(dwc_otg_core_if_t *core_if, uint32_t val)
{
- dctl_data_t dctl;
+ dctl_data_t dctl;
dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
dctl.b.besl_reject = val;
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
}
-uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t * core_if)
+
+uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t *core_if)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
return lpmcfg.b.hird_thres;
}
-void dwc_otg_set_hirdthresh(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_hirdthresh(dwc_otg_core_if_t *core_if, uint32_t val)
{
glpmcfg_data_t lpmcfg;
-
+
if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
DWC_WARN("Wrong valaue for hird_thres\n");
DWC_WARN("hird_thres must be 0-f\n");
- return ;
+ return;
}
-
+
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
lpmcfg.b.hird_thres |= val;
DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
}
-uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t *core_if)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
return lpmcfg.b.prt_sleep_sts;
}
-uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t *core_if)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
return lpmcfg.b.rem_wkup_en;
}
-uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t *core_if)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
return lpmcfg.b.appl_resp;
}
-void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t *core_if, uint32_t val)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
}
-uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t *core_if)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
return lpmcfg.b.hsic_connect;
}
-void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t *core_if, uint32_t val)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
}
-uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t *core_if)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
}
-void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t *core_if, uint32_t val)
{
glpmcfg_data_t lpmcfg;
lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
}
-uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
}
-void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_gotgctl(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
}
-uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
}
-void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
}
-uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
}
-void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
}
-uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
}
-void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
}
-uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
}
-void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
}
-uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
}
-void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_ggpio(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
}
-uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(core_if->host_if->hprt0);
}
-void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_hprt0(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(core_if->host_if->hprt0, val);
}
-uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->guid);
}
-void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
+void dwc_otg_set_guid(dwc_otg_core_if_t *core_if, uint32_t val)
{
DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
}
-uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t *core_if)
{
return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
}
-uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
+uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t *core_if)
{
- return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
+ return ((core_if->otg_ver ==
+ 1) ? (uint16_t) 0x0200 : (uint16_t) 0x0103);
}
/**
*
* @param core_if the pointer to core_if strucure.
*/
-void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
+void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t *core_if)
{
core_if->srp_timer_started = 1;
- DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
+ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */);
}
-void dwc_otg_initiate_srp(void * p)
+void dwc_otg_initiate_srp(void *p)
{
- dwc_otg_core_if_t * core_if = p;
- uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
+ dwc_otg_core_if_t *core_if = p;
+ uint32_t *addr = (uint32_t *)&(core_if->core_global_regs->gotgctl);
gotgctl_data_t mem;
gotgctl_data_t val;
return;
}
- DWC_INFO("Session Request Initated\n"); //NOTICE
+ DWC_INFO("Session Request Initated\n");
mem.d32 = DWC_READ_REG32(addr);
mem.b.sesreq = 1;
DWC_WRITE_REG32(addr, mem.d32);
return;
}
-int dwc_otg_check_haps_status(dwc_otg_core_if_t * core_if)
+int dwc_otg_check_haps_status(dwc_otg_core_if_t *core_if)
{
- int retval = 0;
+ int retval = 0;
- if(DWC_READ_REG32(&core_if->core_global_regs->gsnpsid) == 0xffffffff)
- {
+ if (DWC_READ_REG32(&core_if->core_global_regs->gsnpsid) == 0xffffffff) {
return -1;
- } else {
+ } else {
return retval;
- }
+ }
+
+}
+
+void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
+{
+ gusbcfg_data_t usbcfg = {.d32 = 0 };
+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+ switch (mode) {
+ case USB_MODE_FORCE_HOST:
+ usbcfg.b.force_host_mode = 1;
+ usbcfg.b.force_dev_mode = 0;
+ break;
+ case USB_MODE_FORCE_DEVICE:
+ usbcfg.b.force_host_mode = 0;
+ usbcfg.b.force_dev_mode = 1;
+ break;
+ case USB_MODE_NORMAL:
+ usbcfg.b.force_host_mode = 0;
+ usbcfg.b.force_dev_mode = 0;
+ break;
+ }
+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
}
projects / firefly-linux-kernel-4.4.55.git / blobdiff