}
}
udelay(3);
+ #ifndef CONFIG_DWC_REMOTE_WAKEUP
clk_disable(core_if->otg_dev->phyclk);
clk_disable(core_if->otg_dev->ahbclk);
+ #endif
//power off
return 0;
}
DWC_PRINT("%s, usb device mode\n", __func__);
return 0;
}
+ #ifndef CONFIG_DWC_REMOTE_WAKEUP
clk_enable(core_if->otg_dev->phyclk);
clk_enable(core_if->otg_dev->ahbclk);
-
+ #endif
//partial power-down
//power on
pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
hprt0_data_t hprt0;
-
+
DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
hprt0.d32 = dwc_otg_read_hprt0 (core_if);
dev->coherent_dma_mask = 0;
}
#endif
- DWC_PRINT("dwc_otg_hcd_init everest\n");
// g_dbg_lvl = 0xff;
/*
goto error3;
}
- DWC_PRINT("%s end,everest\n",__func__);
// DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
// dev->bus_id, hcd->self.busnum);
dev->coherent_dma_mask = 0;
}
#endif
- DWC_PRINT("%s everest\n",__func__);
// g_dbg_lvl = 0xff;
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
goto error3;
}
- DWC_PRINT("%s end,everest\n",__func__);
// DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
// dev->bus_id, hcd->self.busnum);
dev->coherent_dma_mask = 0;
}
#endif
- DWC_PRINT("%s everest\n",__func__);
// g_dbg_lvl = 0xff;
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
goto error3;
}
- DWC_PRINT("%s end,everest\n",__func__);
return 0;
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
- DWC_PRINT("dwc_otg_hcd_start! everest\n");
bus = hcd_to_bus(_hcd);
_hcd->state = HC_STATE_RUNNING;
port_status |= (1 << USB_PORT_FEAT_POWER);
if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
- port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
+ port_status |= USB_PORT_STAT_HIGH_SPEED;
else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
- port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
+ port_status |= USB_PORT_STAT_LOW_SPEED;
if (hprt0.b.prttstctl)
port_status |= (1 << USB_PORT_FEAT_TEST);
hprt0.b.prtrst = 1;
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
}
+ spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
- MDELAY (60);
+ // kever @rk 20110712
+ // can not use mdelay(60) while irq disable
+ //MDELAY (60);
+ msleep(60);
+ spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
hprt0.b.prtrst = 0;
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
break;
* periodic assigned schedule.
*/
qh_ptr = qh_ptr->next;
- list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
+ list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
ret_val = DWC_OTG_TRANSACTION_PERIODIC;
}
* non-periodic active schedule.
*/
qh_ptr = qh_ptr->next;
- list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
+ list_move_tail(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
if (ret_val == DWC_OTG_TRANSACTION_NONE) {
ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
* Move the QH from the periodic assigned schedule to
* the periodic queued schedule.
*/
- list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
+ list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
/* done queuing high bandwidth */
_hcd->core_if->queuing_high_bandwidth = 0;