UPSTREAM: usb: dwc3: core: add helper to extract trb type

[firefly-linux-kernel-4.4.55.git] / drivers / usb / dwc3 / core.h

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 11e0c89f45f3ca960dd38c305f920b2a5f9c2c75..85256ba70c1e134cd00fd0f31c7b12fbbb9fcaad 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -153,6 +153,19 @@
 
 /* Bit fields */
 
+/* Global Debug Queue/FIFO Space Available Register */
+#define DWC3_GDBGFIFOSPACE_NUM(n)      ((n) & 0x1f)
+#define DWC3_GDBGFIFOSPACE_TYPE(n)     (((n) << 5) & 0x1e0)
+#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
+
+#define DWC3_TXFIFOQ           1
+#define DWC3_RXFIFOQ           3
+#define DWC3_TXREQQ            5
+#define DWC3_RXREQQ            7
+#define DWC3_RXINFOQ           9
+#define DWC3_DESCFETCHQ                13
+#define DWC3_EVENTQ            15
+
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)        ((n) << 19)
 #define DWC3_GCTL_U2RSTECN     (1 << 16)
@@ -194,6 +207,7 @@
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST   (1 << 31)
 #define DWC3_GUSB3PIPECTL_U2SSINP3OK   (1 << 29)
+#define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28)
 #define DWC3_GUSB3PIPECTL_REQP1P2P3    (1 << 24)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)  ((n) << 19)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK        DWC3_GUSB3PIPECTL_DEP1P2P3(7)
@@ -437,7 +451,6 @@ struct dwc3_event_buffer {
 #define DWC3_EP_DIRECTION_RX   false
 
 #define DWC3_TRB_NUM           256
-#define DWC3_TRB_MASK          (DWC3_TRB_NUM - 1)
 
 /**
  * struct dwc3_ep - device side endpoint representation
@@ -446,8 +459,8 @@ struct dwc3_event_buffer {
  * @started_list: list of started requests on this endpoint
  * @trb_pool: array of transaction buffers
  * @trb_pool_dma: dma address of @trb_pool
- * @free_slot: next slot which is going to be used
- * @busy_slot: first slot which is owned by HW
+ * @trb_enqueue: enqueue 'pointer' into TRB array
+ * @trb_dequeue: dequeue 'pointer' into TRB array
  * @desc: usb_endpoint_descriptor pointer
  * @dwc: pointer to DWC controller
  * @saved_state: ep state saved during hibernation
@@ -467,8 +480,6 @@ struct dwc3_ep {
 
        struct dwc3_trb         *trb_pool;
        dma_addr_t              trb_pool_dma;
-       u32                     free_slot;
-       u32                     busy_slot;
        const struct usb_ss_ep_comp_descriptor *comp_desc;
        struct dwc3             *dwc;
 
@@ -484,6 +495,18 @@ struct dwc3_ep {
        /* This last one is specific to EP0 */
 #define DWC3_EP0_DIR_IN                (1 << 31)
 
+       /*
+        * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
+        * use a u8 type here. If anybody decides to increase number of TRBs to
+        * anything larger than 256 - I can't see why people would want to do
+        * this though - then this type needs to be changed.
+        *
+        * By using u8 types we ensure that our % operator when incrementing
+        * enqueue and dequeue get optimized away by the compiler.
+        */
+       u8                      trb_enqueue;
+       u8                      trb_dequeue;
+
        u8                      number;
        u8                      type;
        u8                      resource_index;
@@ -555,6 +578,7 @@ enum dwc3_link_state {
 #define DWC3_TRB_CTRL_IOC              (1 << 11)
 #define DWC3_TRB_CTRL_SID_SOFN(n)      (((n) & 0xffff) << 14)
 
+#define DWC3_TRBCTL_TYPE(n)            ((n) & (0x3f << 4))
 #define DWC3_TRBCTL_NORMAL             DWC3_TRB_CTRL_TRBCTL(1)
 #define DWC3_TRBCTL_CONTROL_SETUP      DWC3_TRB_CTRL_TRBCTL(2)
 #define DWC3_TRBCTL_CONTROL_STATUS2    DWC3_TRB_CTRL_TRBCTL(3)
@@ -621,12 +645,25 @@ struct dwc3_hwparams {
 /* HWPARAMS7 */
 #define DWC3_RAM1_DEPTH(n)     ((n) & 0xffff)
 
+/**
+ * struct dwc3_request - representation of a transfer request
+ * @request: struct usb_request to be transferred
+ * @list: a list_head used for request queueing
+ * @dep: struct dwc3_ep owning this request
+ * @first_trb_index: index to first trb used by this request
+ * @epnum: endpoint number to which this request refers
+ * @trb: pointer to struct dwc3_trb
+ * @trb_dma: DMA address of @trb
+ * @direction: IN or OUT direction flag
+ * @mapped: true when request has been dma-mapped
+ * @queued: true when request has been queued to HW
+ */
 struct dwc3_request {
        struct usb_request      request;
        struct list_head        list;
        struct dwc3_ep          *dep;
-       u32                     start_slot;
 
+       u8                      first_trb_index;
        u8                      epnum;
        struct dwc3_trb         *trb;
        dma_addr_t              trb_dma;
@@ -665,7 +702,6 @@ struct dwc3_scratchpad_array {
  * @regs: base address for our registers
  * @regs_size: address space size
  * @nr_scratch: number of scratch buffers
- * @num_event_buffers: calculated number of event buffers
  * @u1u2: only used on revisions <1.83a for workaround
  * @maximum_speed: maximum speed requested (mainly for testing purposes)
  * @revision: revision register contents
@@ -752,7 +788,7 @@ struct dwc3 {
        struct platform_device  *xhci;
        struct resource         xhci_resources[DWC3_XHCI_RESOURCES_NUM];
 
-       struct dwc3_event_buffer **ev_buffs;
+       struct dwc3_event_buffer *ev_buf;
        struct dwc3_ep          *eps[DWC3_ENDPOINTS_NUM];
 
        struct usb_gadget       gadget;
@@ -776,7 +812,6 @@ struct dwc3 {
        u32                     gctl;
 
        u32                     nr_scratch;
-       u32                     num_event_buffers;
        u32                     u1u2;
        u32                     maximum_speed;
 
@@ -867,6 +902,7 @@ struct dwc3 {
        unsigned                dis_u3_susphy_quirk:1;
        unsigned                dis_u2_susphy_quirk:1;
        unsigned                dis_enblslpm_quirk:1;
+       unsigned                dis_rxdet_inp3_quirk:1;
 
        unsigned                tx_de_emphasis_quirk:1;
        unsigned                tx_de_emphasis:2;
@@ -1019,6 +1055,7 @@ struct dwc3_gadget_ep_cmd_params {
 
 /* prototypes */
 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
+u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
 
 /* check whether we are on the DWC_usb31 core */
 static inline bool dwc3_is_usb31(struct dwc3 *dwc)