}
pllcalparam;
-
logical_chip_type_t getChipType(void)
{
unsigned short physicalID;
return chip;
}
-inline unsigned int calcPLL(pll_value_t *pPLL)
+static inline unsigned int calcPLL(pll_value_t *pPLL)
{
return (pPLL->inputFreq * pPLL->M / pPLL->N / (1 << pPLL->OD) /
(1 << pPLL->POD));
}
-unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
+static unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
unsigned int ulPllReg = 0;
return calcPLL(pPLL);
}
-
-unsigned int getChipClock(void)
+static unsigned int getChipClock(void)
{
pll_value_t pll;
#if 1
return getPllValue(MXCLK_PLL, &pll);
}
-
/*
* This function set up the main chip clock.
*
* Input: Frequency to be set.
*/
-void setChipClock(unsigned int frequency)
+static void setChipClock(unsigned int frequency)
{
pll_value_t pll;
unsigned int ulActualMxClk;
}
}
-
-
-void setMemoryClock(unsigned int frequency)
+static void setMemoryClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
#if 1
frequency = MHz(336);
/* Calculate the divisor */
- divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
+ divisor = (unsigned int)roundedDiv(getChipClock(), frequency);
/* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE);
}
}
-
/*
* This function set up the master clock (MCLK).
*
* NOTE:
* The maximum frequency the engine can run is 168MHz.
*/
-void setMasterClock(unsigned int frequency)
+static void setMasterClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
#if 1
frequency = MHz(190);
/* Calculate the divisor */
- divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
+ divisor = (unsigned int)roundedDiv(getChipClock(), frequency);
/* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE);
}
}
-
unsigned int ddk750_getVMSize(void)
{
unsigned int reg;
if (pll->clockType != MXCLK_PLL) {
xparm = &xparm_PIXEL[0];
- xcnt = sizeof(xparm_PIXEL)/sizeof(xparm_PIXEL[0]);
+ xcnt = ARRAY_SIZE(xparm_PIXEL);
} else {
xparm = &xparm_MXCLK[0];
- xcnt = sizeof(xparm_MXCLK)/sizeof(xparm_MXCLK[0]);
+ xcnt = ARRAY_SIZE(xparm_MXCLK);
}
for (d = xcnt - 1; d >= 0; d--) {
X = xparm[d].value;
- M = quo*X;
+ M = quo * X;
M += fl_quo * X / 10000;
/* round step */
- M += (fl_quo*X % 10000) > 5000?1:0;
+ M += (fl_quo * X % 10000) > 5000 ? 1 : 0;
if (M < 256 && M > 0) {
unsigned int diff;
return ret;
}
-unsigned int calcPllValue2(
-unsigned int ulRequestClk, /* Required pixel clock in Hz unit */
-pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
-)
-{
- unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower;
- unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */
- unsigned int ret;
- /* Init PLL structure to know states */
- pPLL->M = 0;
- pPLL->N = 0;
- pPLL->OD = 0;
- pPLL->POD = 0;
-
- /* Sanity check: None at the moment */
-
- /* Convert everything in Khz range in order to avoid calculation overflow */
- pPLL->inputFreq /= 1000;
- ulRequestClk /= 1000;
-
-#ifndef VALIDATION_CHIP
- /* The maximum of post divider is 8. */
- for (POD = 0; POD <= 3; POD++)
-#endif
- {
-
-#ifndef VALIDATION_CHIP
- /* MXCLK_PLL does not have post divider. */
- if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))
- break;
-#endif
-
- /* Work out 2 to the power of POD */
- podPower = 1 << POD;
-
- /* OD has only 2 bits [15:14] and its value must between 0 to 3 */
- for (OD = 0; OD <= 3; OD++) {
- /* Work out 2 to the power of OD */
- odPower = 1 << OD;
-
-#ifdef VALIDATION_CHIP
- if (odPower > 4)
- podPower = 4;
- else
- podPower = odPower;
-#endif
-
- /* N has 4 bits [11:8] and its value must between 2 and 15.
- The N == 1 will behave differently --> Result is not correct. */
- for (N = 2; N <= 15; N++) {
- /* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)
- In the following steps, we try to work out a best M value given the others are known.
- To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
- */
- M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq;
- M = roundedDiv(M, 1000);
-
- /* M field has only 8 bits, reject value bigger than 8 bits */
- if (M < 256) {
- /* Calculate the actual clock for a given M & N */
- pllClk = pPLL->inputFreq * M / N / odPower / podPower;
-
- /* How much are we different from the requirement */
- diff = absDiff(pllClk, ulRequestClk);
-
- if (diff < bestDiff) {
- bestDiff = diff;
-
- /* Store M and N values */
- pPLL->M = M;
- pPLL->N = N;
- pPLL->OD = OD;
-
-#ifdef VALIDATION_CHIP
- if (OD > 2)
- POD = 2;
- else
- POD = OD;
-#endif
-
- pPLL->POD = POD;
- }
- }
- }
- }
- }
-
- /* Restore input frequency from Khz to hz unit */
- ulRequestClk *= 1000;
- pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
-
- /* Return actual frequency that the PLL can set */
- ret = calcPLL(pPLL);
- return ret;
-}
-
-
-
-
-
unsigned int formatPllReg(pll_value_t *pPLL)
{
unsigned int ulPllReg = 0;
projects / firefly-linux-kernel-4.4.55.git / blobdiff