{
u32 val;
- clk_enable(nvec->i2c_clk);
+ clk_prepare_enable(nvec->i2c_clk);
tegra_periph_reset_assert(nvec->i2c_clk);
udelay(2);
enable_irq(nvec->irq);
- clk_disable(nvec->i2c_clk);
+ clk_disable_unprepare(nvec->i2c_clk);
}
#ifdef CONFIG_PM_SLEEP
{
disable_irq(nvec->irq);
writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
- clk_disable(nvec->i2c_clk);
+ clk_disable_unprepare(nvec->i2c_clk);
}
#endif
tegra_init_i2c_slave(nvec);
- clk_enable(i2c_clk);
+ clk_prepare_enable(i2c_clk);
/* enable event reporting */