mmc: core: use default generic cmd6 timeout for flushing cache

[firefly-linux-kernel-4.4.55.git] / drivers / spi / spi-rockchip-dma.c

diff --git a/drivers/spi/spi-rockchip-dma.c b/drivers/spi/spi-rockchip-dma.c
index 750d598f2b3e56e73cfac491f1489adfd7e921e5..6952201406cdd2d8cef84ccd316bcc2003d45099 100755 (executable)
--- a/drivers/spi/spi-rockchip-dma.c
+++ b/drivers/spi/spi-rockchip-dma.c
@@ -68,7 +68,6 @@ static int mid_spi_dma_init(struct dw_spi *dws)
 {
        struct spi_dma *dw_dma = dws->dma_priv;
        struct spi_dma_slave *rxs, *txs;
-       dma_cap_mask_t mask;
        
        DBG_SPI("%s:start\n",__func__);
 
@@ -87,10 +86,10 @@ static int mid_spi_dma_init(struct dw_spi *dws)
 
        /* 2. Init tx channel */
        dws->txchan = dma_request_slave_channel(dws->parent_dev, "tx");
-       if (!dws->rxchan)
+       if (!dws->txchan)
        {
-               dev_err(dws->parent_dev, "Failed to get RX DMA channel\n");
-               goto err_exit;
+               dev_err(dws->parent_dev, "Failed to get TX DMA channel\n");
+               goto free_rxchan;
        }
        txs = &dw_dma->dmas_tx;
        dws->txchan->private = txs;
@@ -151,10 +150,10 @@ static void dw_spi_dma_rxcb(void *arg)
        /* If the other done */
        if (!(dws->state & TXBUSY))
        {
-               complete(&dws->xfer_completion);        
-               DBG_SPI("%s:complete\n", __FUNCTION__);         
                //DMA could not lose intterupt
                dw_spi_xfer_done(dws);
+               complete(&dws->xfer_completion);
+               DBG_SPI("%s:complete\n", __FUNCTION__);
        }
 
 }
@@ -185,13 +184,12 @@ static void dw_spi_dma_txcb(void *arg)
        spin_unlock_irqrestore(&dws->lock, flags);
        
        /* If the other done */
-       if (!(dws->state & RXBUSY)) 
+       if (!(dws->state & RXBUSY))
        {
-               complete(&dws->xfer_completion);                
-               DBG_SPI("%s:complete\n", __FUNCTION__);
-
                //DMA could not lose intterupt
                dw_spi_xfer_done(dws);
+               complete(&dws->xfer_completion);
+               DBG_SPI("%s:complete\n", __FUNCTION__);
        }
 
 }
@@ -202,7 +200,6 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
        struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
        struct dma_chan *txchan, *rxchan;
        struct dma_slave_config txconf, rxconf;
-       u16 dma_ctrl = 0;
        int ret = 0;
        
        enum dma_slave_buswidth width;
@@ -255,7 +252,7 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
                /* 2. Prepare the TX dma transfer */
                txconf.direction = DMA_MEM_TO_DEV;
                txconf.dst_addr = dws->tx_dma_addr;
-               txconf.dst_maxburst = dws->dma_width;
+               txconf.dst_maxburst = dws->dmatdlr;//dws->dma_width;
                //txconf.src_addr_width = width;
                txconf.dst_addr_width = width;
                //txconf.device_fc = false;
@@ -268,8 +265,11 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
                
                memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
                dws->tx_sgl.dma_address = dws->tx_dma;
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+               dws->tx_sgl.dma_length = dws->len;
+#else
                dws->tx_sgl.length = dws->len;
-
+#endif
                txdesc = dmaengine_prep_slave_sg(txchan,
                                        &dws->tx_sgl,
                                        1,
@@ -279,7 +279,8 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
                txdesc->callback = dw_spi_dma_txcb;
                txdesc->callback_param = dws;
 
-               DBG_SPI("%s:dst_addr=0x%p,tx_dma=0x%p,len=%d,burst=%d,width=%d\n",__func__,(int *)dws->tx_dma_addr, (int *)dws->tx_dma, dws->len,dws->dma_width, width);
+               DBG_SPI("%s:dst_addr=0x%p,tx_dma=0x%p,len=%ld,burst=%d,width=%d\n"
+                       ,__func__,(int *)dws->tx_dma_addr, (int *)dws->tx_dma, (long)dws->len,txconf.dst_maxburst, width);
        }
 
        if (dws->rx)
@@ -287,7 +288,7 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
                /* 3. Prepare the RX dma transfer */
                rxconf.direction = DMA_DEV_TO_MEM;
                rxconf.src_addr = dws->rx_dma_addr;
-               rxconf.src_maxburst = dws->dma_width; 
+               rxconf.src_maxburst = dws->dmardlr + 1;//dws->dma_width;
                //rxconf.dst_addr_width = width;
                rxconf.src_addr_width = width;
                //rxconf.device_fc = false;
@@ -300,7 +301,11 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 
                memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
                dws->rx_sgl.dma_address = dws->rx_dma;
-               dws->rx_sgl.length = dws->len;                          
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+               dws->rx_sgl.dma_length = dws->len;                              
+#else
+               dws->rx_sgl.length = dws->len;
+#endif
 
                rxdesc = dmaengine_prep_slave_sg(rxchan,
                                        &dws->rx_sgl,
@@ -310,8 +315,12 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
                rxdesc->callback = dw_spi_dma_rxcb;
                rxdesc->callback_param = dws;
                
-               DBG_SPI("%s:src_addr=0x%p,rx_dma=0x%p,len=%d,burst=%d,width=%d\n",__func__, (int *)dws->rx_dma_addr, (int *)dws->rx_dma, dws->len, dws->dma_width, width);
+               DBG_SPI("%s:src_addr=0x%p,rx_dma=0x%p,len=%ld,burst=%d,width=%d\n"
+                       ,__func__, (int *)dws->rx_dma_addr, (int *)dws->rx_dma, (long)dws->len, rxconf.src_maxburst, width);
        }
+
+       if(!dws->tx)
+       spi_enable_chip(dws, 1);
        
        /* rx must be started before tx due to spi instinct */  
        if (dws->rx)