u8 cs; /* chip select pin */\r
u8 n_bytes; /* current is a 1/2/4 byte op */\r
u8 tmode; /* TR/TO/RO/EEPROM */\r
+ u8 mode; /* ??? */\r
u8 type; /* SPI/SSP/MicroWire */\r
\r
u8 poll_mode; /* 1 means use poll mode */\r
-\r
+ u8 slave_enable;\r
u32 dma_width;\r
u32 rx_threshold;\r
u32 tx_threshold;\r
}\r
#endif\r
\r
+#if 0\r
static void spi_dump_regs(struct rk29xx_spi *dws) {\r
DBG("MRST SPI0 registers:\n");\r
DBG("=================================\n");\r
DBG("=================================\n");\r
\r
}\r
+#endif\r
\r
#ifdef CONFIG_DEBUG_FS\r
static int spi_show_regs_open(struct inode *inode, struct file *file)\r
static void wait_till_not_busy(struct rk29xx_spi *dws)\r
{\r
unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
-\r
+ //if spi was slave, it is SR_BUSY always. \r
+ if(dws->cur_chip) {\r
+ if(dws->cur_chip->slave_enable == 1)\r
+ return;\r
+ }\r
+ \r
while (time_before(jiffies, end)) {\r
if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
return;\r
rk29xx_writel(dws, SPIM_SER, 0);\r
return;\r
#else\r
+ \r
+ #error "Warning: not support"\r
struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
\r
dws->prev_chip = dws->cur_chip;\r
dws->cur_chip = NULL;\r
dws->dma_mapped = 0;\r
+\r
\r
/*it is important to close intterrupt*/\r
spi_mask_intr(dws, 0xff);\r
\r
cr0 &= ~(0x3 << SPI_MODE_OFFSET); \r
cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
+ cr0 &= ~(0x1 << SPI_OPMOD_OFFSET); \r
+ cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
+ cr0 |= ((chip->slave_enable & 1) << SPI_OPMOD_OFFSET);\r
} \r
\r
/*\r
spi_chip_sel(dws, spi->chip_select);\r
\r
rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
- spi_enable_chip(dws, 1);\r
-\r
+ \r
if (txint_level)\r
rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
+ spi_enable_chip(dws, 1); \r
+ \r
if (rxint_level)\r
rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
/* Set the interrupt mask, for poll mode just diable all int */\r
\r
cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
+ cr0 &= ~(0x1 << SPI_OPMOD_OFFSET); \r
+ cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
+ cr0 |= ((chip->slave_enable & 1) << SPI_OPMOD_OFFSET);\r
}\r
\r
/*\r
chip->tmode = SPI_TMOD_TO;\r
\r
cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
+ cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
+ cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
}\r
\r
\r
chip->poll_mode = chip_info->poll_mode;\r
chip->type = chip_info->type;\r
-\r
+ chip->slave_enable = chip_info->slave_enable;\r
chip->rx_threshold = 0;\r
chip->tx_threshold = 0;\r
\r