#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
+#include <linux/device.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>
SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
SIS_PMR = 0x90, /* port mapping register */
- SIS_PMR_COMBINED = 0x30,
+ SIS_PMR_COMBINED = 0x30,
/* random bits */
SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
.ordered_flush = 1,
};
-static struct ata_port_operations sis_ops = {
+static const struct ata_port_operations sis_ops = {
.port_disable = ata_port_disable,
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
{
unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
- if (port_no)
+ if (port_no) {
if (device == 0x182)
addr += SIS182_SATA1_OFS;
else
addr += SIS180_SATA1_OFS;
+ }
+
return addr;
}
{
struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
- u32 val, val2;
+ u32 val, val2 = 0;
u8 pmr;
if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
return 0xffffffff;
pci_read_config_byte(pdev, SIS_PMR, &pmr);
-
+
pci_read_config_dword(pdev, cfg_addr, &val);
- if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
+ if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
return val|val2;
return;
pci_read_config_byte(pdev, SIS_PMR, &pmr);
-
+
pci_write_config_dword(pdev, cfg_addr, val);
if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
- u32 val,val2;
+ u32 val, val2 = 0;
u8 pmr;
if (sc_reg > SCR_CONTROL)
val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
- val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
+ val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
- return val|val2;
+ return val | val2;
}
static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
return;
pci_read_config_byte(pdev, SIS_PMR, &pmr);
-
+
if (ap->flags & SIS_FLAG_CFGSCR)
sis_scr_cfg_write(ap, sc_reg, val);
else {
}
}
-/* move to PCI layer, integrate w/ MSI stuff */
-static void pci_enable_intx(struct pci_dev *pdev)
-{
- u16 pci_command;
-
- pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
- if (pci_command & PCI_COMMAND_INTX_DISABLE) {
- pci_command &= ~PCI_COMMAND_INTX_DISABLE;
- pci_write_config_word(pdev, PCI_COMMAND, pci_command);
- }
-}
-
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
+ static int printed_version;
struct ata_probe_ent *probe_ent = NULL;
int rc;
u32 genctl;
u8 pmr;
u8 port2_start;
+ if (!printed_version++)
+ dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
+
rc = pci_enable_device(pdev);
if (rc)
return rc;
goto err_out_regions;
ppi = &sis_port_info;
- probe_ent = ata_pci_init_native_mode(pdev, &ppi);
+ probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
if (!probe_ent) {
rc = -ENOMEM;
goto err_out_regions;
pci_read_config_byte(pdev, SIS_PMR, &pmr);
if (ent->device != 0x182) {
if ((pmr & SIS_PMR_COMBINED) == 0) {
- printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in SATA mode\n");
- port2_start=0x64;
+ dev_printk(KERN_INFO, &pdev->dev,
+ "Detected SiS 180/181 chipset in SATA mode\n");
+ port2_start = 64;
}
else {
- printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in combined mode\n");
+ dev_printk(KERN_INFO, &pdev->dev,
+ "Detected SiS 180/181 chipset in combined mode\n");
port2_start=0;
}
}
else {
- printk(KERN_INFO "sata_sis: Detected SiS 182 chipset\n");
+ dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n");
port2_start = 0x20;
}
}
pci_set_master(pdev);
- pci_enable_intx(pdev);
+ pci_intx(pdev, 1);
/* FIXME: check ata_device_add return value */
ata_device_add(probe_ent);