ret = clk_prepare_enable(info->clk);
if (ret)
- goto err_enable_clk;
+ return ret;
/*
* According to the manual we should be able to let RTTR be zero
* and then a default diviser for a 32.768KHz clock is used.
return 0;
err_dev:
clk_disable_unprepare(info->clk);
-err_enable_clk:
- platform_set_drvdata(pdev, NULL);
return ret;
}
{
struct sa1100_rtc *info = platform_get_drvdata(pdev);
- if (info) {
+ if (info)
clk_disable_unprepare(info->clk);
- platform_set_drvdata(pdev, NULL);
- }
return 0;
}