PCI: rockchip: remove redundant platform data assignment

[firefly-linux-kernel-4.4.55.git] / drivers / pci / host / pcie-rockchip.c

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 390e8dffe6f948eafbed8a74f22363e1c0d1d3a1..8ada33767834e9fe81abb91c2bce6454592dcf98 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -125,6 +125,7 @@
 #define   PCIE_CORE_INT_CT                     BIT(11)
 #define   PCIE_CORE_INT_UTC                    BIT(18)
 #define   PCIE_CORE_INT_MMVC                   BIT(19)
+#define PCIE_CORE_CONFIG_VENDOR                (PCIE_CORE_CTRL_MGMT_BASE + 0x44)
 #define PCIE_CORE_INT_MASK             (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
 #define PCIE_RC_BAR_CONF               (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
 
@@ -138,7 +139,6 @@
                 PCIE_CORE_INT_MMVC)
 
 #define PCIE_RC_CONFIG_BASE            0xa00000
-#define PCIE_RC_CONFIG_VENDOR          (PCIE_RC_CONFIG_BASE + 0x00)
 #define PCIE_RC_CONFIG_RID_CCR         (PCIE_RC_CONFIG_BASE + 0x08)
 #define   PCIE_RC_CONFIG_SCC_SHIFT             16
 #define PCIE_RC_CONFIG_DCR             (PCIE_RC_CONFIG_BASE + 0xc4)
@@ -189,6 +189,10 @@
           PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
 #define PCIE_LINK_IS_L2(x) \
        (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
+#define PCIE_LINK_UP(x) \
+       (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_LINK_IS_GEN2(x) \
+       (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G)
 
 #define RC_REGION_0_ADDR_TRANS_H               0x00000000
 #define RC_REGION_0_ADDR_TRANS_L               0x00000000
@@ -462,7 +466,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        struct device *dev = rockchip->dev;
        int err;
        u32 status;
-       unsigned long timeout;
 
        gpiod_set_value(rockchip->ep_gpio, 0);
 
@@ -603,23 +606,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        gpiod_set_value(rockchip->ep_gpio, 1);
 
        /* 500ms timeout value should be enough for Gen1/2 training */
-       timeout = jiffies + msecs_to_jiffies(500);
-
-       for (;;) {
-               status = rockchip_pcie_read(rockchip,
-                                           PCIE_CLIENT_BASIC_STATUS1);
-               if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
-                   PCIE_CLIENT_LINK_STATUS_UP) {
-                       dev_dbg(dev, "PCIe link training gen1 pass!\n");
-                       break;
-               }
-
-               if (time_after(jiffies, timeout)) {
-                       dev_err(dev, "PCIe link training gen1 timeout!\n");
-                       return -ETIMEDOUT;
-               }
-
-               msleep(20);
+       err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
+                                status, PCIE_LINK_UP(status), 20,
+                                500 * USEC_PER_MSEC);
+       if (err) {
+               dev_err(dev, "PCIe link training gen1 timeout!\n");
+               return -ETIMEDOUT;
        }
 
        if (rockchip->link_gen == 2) {
@@ -631,22 +623,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                status |= PCI_EXP_LNKCTL_RL;
                rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
 
-               timeout = jiffies + msecs_to_jiffies(500);
-               for (;;) {
-                       status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-                       if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
-                           PCIE_CORE_PL_CONF_SPEED_5G) {
-                               dev_dbg(dev, "PCIe link training gen2 pass!\n");
-                               break;
-                       }
-
-                       if (time_after(jiffies, timeout)) {
-                               dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
-                               break;
-                       }
-
-                       msleep(20);
-               }
+               err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
+                                        status, PCIE_LINK_IS_GEN2(status), 20,
+                                        500 * USEC_PER_MSEC);
+               if (err)
+                       dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
        }
 
        /* Check the final link width from negotiated lane counter from MGMT */
@@ -656,7 +637,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        dev_dbg(dev, "current link width is x%d\n", status);
 
        rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
-                           PCIE_RC_CONFIG_VENDOR);
+                           PCIE_CORE_CONFIG_VENDOR);
        rockchip_pcie_write(rockchip,
                            PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
                            PCIE_RC_CONFIG_RID_CCR);
@@ -667,7 +648,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
 
        /* Clear L0s from RC's link cap */
-       if (of_property_read_bool(dev->of_node, "quirk,apsm-no-l0s")) {
+       if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
                status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
                status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
                rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
@@ -1167,6 +1148,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
 
 static int rockchip_cfg_atu(struct rockchip_pcie *rockchip)
 {
+       struct device *dev = rockchip->dev;
        int offset;
        int err;
        int reg_no;
@@ -1179,15 +1161,14 @@ static int rockchip_cfg_atu(struct rockchip_pcie *rockchip)
                                                (reg_no << 20),
                                                0);
                if (err) {
-                       dev_err(rockchip->dev,
-                                       "program RC mem outbound ATU failed\n");
+                       dev_err(dev, "program RC mem outbound ATU failed\n");
                        return err;
                }
        }
 
        err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
        if (err) {
-               dev_err(rockchip->dev, "program RC mem inbound ATU failed\n");
+               dev_err(dev, "program RC mem inbound ATU failed\n");
                return err;
        }
 
@@ -1201,8 +1182,7 @@ static int rockchip_cfg_atu(struct rockchip_pcie *rockchip)
                                                (reg_no << 20),
                                                0);
                if (err) {
-                       dev_err(rockchip->dev,
-                                       "program RC io outbound ATU failed\n");
+                       dev_err(dev, "program RC io outbound ATU failed\n");
                        return err;
                }
        }
@@ -1237,7 +1217,7 @@ static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
        return 0;
 }
 
-static int rockchip_pcie_suspend_noirq(struct device *dev)
+static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev)
 {
        struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
        int ret;
@@ -1264,7 +1244,7 @@ static int rockchip_pcie_suspend_noirq(struct device *dev)
        return ret;
 }
 
-static int rockchip_pcie_resume_noirq(struct device *dev)
+static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
 {
        struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
        int err;
@@ -1350,8 +1330,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
        if (err)
                goto err_vpcie;
 
-       platform_set_drvdata(pdev, rockchip);
-
        rockchip_pcie_enable_interrupts(rockchip);
 
        err = rockchip_pcie_init_irq_domain(rockchip);