rt2x00: Code style cleanup in rt2800lib.c

[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rt2x00 / rt2800lib.c

diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 88455b1b9fe05b299aff2cc667d3d90e7822855a..d745c32a73612cae107cbe48a03db1f229f51a98 100644 (file)
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -221,6 +221,67 @@ static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
        mutex_unlock(&rt2x00dev->csr_mutex);
 }
 
+static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
+{
+       u32 reg;
+       int i, count;
+
+       rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
+       if (rt2x00_get_field32(reg, WLAN_EN))
+               return 0;
+
+       rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
+       rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
+       rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
+       rt2x00_set_field32(&reg, WLAN_EN, 1);
+       rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
+
+       udelay(REGISTER_BUSY_DELAY);
+
+       count = 0;
+       do {
+               /*
+                * Check PLL_LD & XTAL_RDY.
+                */
+               for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
+                       rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
+                       if (rt2x00_get_field32(reg, PLL_LD) &&
+                           rt2x00_get_field32(reg, XTAL_RDY))
+                               break;
+                       udelay(REGISTER_BUSY_DELAY);
+               }
+
+               if (i >= REGISTER_BUSY_COUNT) {
+
+                       if (count >= 10)
+                               return -EIO;
+
+                       rt2800_register_write(rt2x00dev, 0x58, 0x018);
+                       udelay(REGISTER_BUSY_DELAY);
+                       rt2800_register_write(rt2x00dev, 0x58, 0x418);
+                       udelay(REGISTER_BUSY_DELAY);
+                       rt2800_register_write(rt2x00dev, 0x58, 0x618);
+                       udelay(REGISTER_BUSY_DELAY);
+                       count++;
+               } else {
+                       count = 0;
+               }
+
+               rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
+               rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
+               rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
+               rt2x00_set_field32(&reg, WLAN_RESET, 1);
+               rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
+               udelay(10);
+               rt2x00_set_field32(&reg, WLAN_RESET, 0);
+               rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
+               udelay(10);
+               rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
+       } while (count != 0);
+
+       return 0;
+}
+
 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
                        const u8 command, const u8 token,
                        const u8 arg0, const u8 arg1)
@@ -400,6 +461,13 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 {
        unsigned int i;
        u32 reg;
+       int retval;
+
+       if (rt2x00_rt(rt2x00dev, RT3290)) {
+               retval = rt2800_enable_wlan_rt3290(rt2x00dev);
+               if (retval)
+                       return -EBUSY;
+       }
 
        /*
         * If driver doesn't wake up firmware here,
@@ -855,8 +923,8 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
                rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
                return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
        } else {
-               rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-               return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
+               rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+               return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
        }
 }
 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
@@ -1502,10 +1570,10 @@ static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
                rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
                                   eesk_pin, 0);
 
-       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
-       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
+       rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
+       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 }
 
 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
@@ -1547,6 +1615,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
        case 1:
                if (rt2x00_rt(rt2x00dev, RT3070) ||
                    rt2x00_rt(rt2x00dev, RT3090) ||
+                   rt2x00_rt(rt2x00dev, RT3352) ||
                    rt2x00_rt(rt2x00dev, RT3390)) {
                        rt2x00_eeprom_read(rt2x00dev,
                                           EEPROM_NIC_CONF1, &eeprom);
@@ -1927,13 +1996,13 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
                rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
        }
 
-       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
+       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
        if (rf->channel <= 14)
-               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
+               rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
        else
-               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
-       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+               rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
+       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 
        rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
        rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
@@ -1985,6 +2054,60 @@ static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
        }
 }
 
+static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
+                                        struct ieee80211_conf *conf,
+                                        struct rf_channel *rf,
+                                        struct channel_info *info)
+{
+       u8 rfcsr;
+
+       rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
+       rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
+
+       rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
+       rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
+       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
+
+       if (info->default_power1 > POWER_BOUND)
+               rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
+       else
+               rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
+
+       if (info->default_power2 > POWER_BOUND)
+               rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
+       else
+               rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
+
+       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
+       if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
+               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
+       else
+               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
+
+       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
+
+       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
+       rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
+       rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
+
+       if ( rt2x00dev->default_ant.tx_chain_num == 2 )
+               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
+       else
+               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
+
+       if ( rt2x00dev->default_ant.rx_chain_num == 2 )
+               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
+       else
+               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
+
+       rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
+       rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
+
+       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
+
+       rt2800_rfcsr_write(rt2x00dev, 31, 80);
+}
+
 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
                                         struct ieee80211_conf *conf,
                                         struct rf_channel *rf,
@@ -2114,6 +2237,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
        case RF3290:
                rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
                break;
+       case RF3322:
+               rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
+               break;
        case RF5360:
        case RF5370:
        case RF5372:
@@ -2126,6 +2252,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
        }
 
        if (rt2x00_rf(rt2x00dev, RF3290) ||
+           rt2x00_rf(rt2x00dev, RF3322) ||
            rt2x00_rf(rt2x00dev, RF5360) ||
            rt2x00_rf(rt2x00dev, RF5370) ||
            rt2x00_rf(rt2x00dev, RF5372) ||
@@ -2144,10 +2271,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
        /*
         * Change BBP settings
         */
-       rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
-       rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
-       rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
-       rt2800_bbp_write(rt2x00dev, 86, 0);
+       if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_bbp_write(rt2x00dev, 27, 0x0);
+               rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
+               rt2800_bbp_write(rt2x00dev, 27, 0x20);
+               rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
+       } else {
+               rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
+               rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
+               rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
+               rt2800_bbp_write(rt2x00dev, 86, 0);
+       }
 
        if (rf->channel <= 14) {
                if (!rt2x00_rt(rt2x00dev, RT5390) &&
@@ -2242,6 +2376,15 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
        rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
        rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
        rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
+
+       /*
+        * Clear update flag
+        */
+       if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_bbp_read(rt2x00dev, 49, &bbp);
+               rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
+               rt2800_bbp_write(rt2x00dev, 49, bbp);
+       }
 }
 
 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
@@ -2753,23 +2896,32 @@ EXPORT_SYMBOL_GPL(rt2800_link_stats);
 
 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
 {
+       u8 vgc;
+
        if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
                if (rt2x00_rt(rt2x00dev, RT3070) ||
                    rt2x00_rt(rt2x00dev, RT3071) ||
                    rt2x00_rt(rt2x00dev, RT3090) ||
                    rt2x00_rt(rt2x00dev, RT3290) ||
                    rt2x00_rt(rt2x00dev, RT3390) ||
+                   rt2x00_rt(rt2x00dev, RT3572) ||
                    rt2x00_rt(rt2x00dev, RT5390) ||
                    rt2x00_rt(rt2x00dev, RT5392))
-                       return 0x1c + (2 * rt2x00dev->lna_gain);
+                       vgc = 0x1c + (2 * rt2x00dev->lna_gain);
                else
-                       return 0x2e + rt2x00dev->lna_gain;
+                       vgc = 0x2e + rt2x00dev->lna_gain;
+       } else { /* 5GHZ band */
+               if (rt2x00_rt(rt2x00dev, RT3572))
+                       vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
+               else {
+                       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
+                               vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
+                       else
+                               vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
+               }
        }
 
-       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
-               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
-       else
-               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
+       return vgc;
 }
 
 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
@@ -2930,11 +3082,15 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
                rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
+       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
+               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
+               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
        } else if (rt2x00_rt(rt2x00dev, RT3572)) {
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
        } else if (rt2x00_rt(rt2x00dev, RT5390) ||
-                          rt2x00_rt(rt2x00dev, RT5392)) {
+                  rt2x00_rt(rt2x00dev, RT5392)) {
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
                rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
@@ -3310,6 +3466,11 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                     rt2800_wait_bbp_ready(rt2x00dev)))
                return -EACCES;
 
+       if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_bbp_write(rt2x00dev, 3, 0x00);
+               rt2800_bbp_write(rt2x00dev, 4, 0x50);
+       }
+
        if (rt2x00_rt(rt2x00dev, RT3290) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392)) {
@@ -3320,15 +3481,20 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 
        if (rt2800_is_305x_soc(rt2x00dev) ||
            rt2x00_rt(rt2x00dev, RT3290) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT3572) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 31, 0x08);
 
+       if (rt2x00_rt(rt2x00dev, RT3352))
+               rt2800_bbp_write(rt2x00dev, 47, 0x48);
+
        rt2800_bbp_write(rt2x00dev, 65, 0x2c);
        rt2800_bbp_write(rt2x00dev, 66, 0x38);
 
        if (rt2x00_rt(rt2x00dev, RT3290) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 68, 0x0b);
@@ -3337,6 +3503,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                rt2800_bbp_write(rt2x00dev, 69, 0x16);
                rt2800_bbp_write(rt2x00dev, 73, 0x12);
        } else if (rt2x00_rt(rt2x00dev, RT3290) ||
+                  rt2x00_rt(rt2x00dev, RT3352) ||
                   rt2x00_rt(rt2x00dev, RT5390) ||
                   rt2x00_rt(rt2x00dev, RT5392)) {
                rt2800_bbp_write(rt2x00dev, 69, 0x12);
@@ -3368,15 +3535,17 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
        } else if (rt2800_is_305x_soc(rt2x00dev)) {
                rt2800_bbp_write(rt2x00dev, 78, 0x0e);
                rt2800_bbp_write(rt2x00dev, 80, 0x08);
-       } else {
-               rt2800_bbp_write(rt2x00dev, 81, 0x37);
-       }
-
-       if (rt2x00_rt(rt2x00dev, RT3290)) {
+       } else if (rt2x00_rt(rt2x00dev, RT3290)) {
                rt2800_bbp_write(rt2x00dev, 74, 0x0b);
                rt2800_bbp_write(rt2x00dev, 79, 0x18);
                rt2800_bbp_write(rt2x00dev, 80, 0x09);
                rt2800_bbp_write(rt2x00dev, 81, 0x33);
+       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_bbp_write(rt2x00dev, 78, 0x0e);
+               rt2800_bbp_write(rt2x00dev, 80, 0x08);
+               rt2800_bbp_write(rt2x00dev, 81, 0x37);
+       } else {
+               rt2800_bbp_write(rt2x00dev, 81, 0x37);
        }
 
        rt2800_bbp_write(rt2x00dev, 82, 0x62);
@@ -3397,18 +3566,21 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                rt2800_bbp_write(rt2x00dev, 84, 0x99);
 
        if (rt2x00_rt(rt2x00dev, RT3290) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 86, 0x38);
        else
                rt2800_bbp_write(rt2x00dev, 86, 0x00);
 
-       if (rt2x00_rt(rt2x00dev, RT5392))
+       if (rt2x00_rt(rt2x00dev, RT3352) ||
+           rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 88, 0x90);
 
        rt2800_bbp_write(rt2x00dev, 91, 0x04);
 
        if (rt2x00_rt(rt2x00dev, RT3290) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 92, 0x02);
@@ -3425,6 +3597,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
            rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
            rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
            rt2x00_rt(rt2x00dev, RT3290) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT3572) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392) ||
@@ -3434,6 +3607,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                rt2800_bbp_write(rt2x00dev, 103, 0x00);
 
        if (rt2x00_rt(rt2x00dev, RT3290) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 104, 0x92);
@@ -3442,6 +3616,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                rt2800_bbp_write(rt2x00dev, 105, 0x01);
        else if (rt2x00_rt(rt2x00dev, RT3290))
                rt2800_bbp_write(rt2x00dev, 105, 0x1c);
+       else if (rt2x00_rt(rt2x00dev, RT3352))
+               rt2800_bbp_write(rt2x00dev, 105, 0x34);
        else if (rt2x00_rt(rt2x00dev, RT5390) ||
                         rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 105, 0x3c);
@@ -3451,11 +3627,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
        if (rt2x00_rt(rt2x00dev, RT3290) ||
            rt2x00_rt(rt2x00dev, RT5390))
                rt2800_bbp_write(rt2x00dev, 106, 0x03);
+       else if (rt2x00_rt(rt2x00dev, RT3352))
+               rt2800_bbp_write(rt2x00dev, 106, 0x05);
        else if (rt2x00_rt(rt2x00dev, RT5392))
                rt2800_bbp_write(rt2x00dev, 106, 0x12);
        else
                rt2800_bbp_write(rt2x00dev, 106, 0x35);
 
+       if (rt2x00_rt(rt2x00dev, RT3352))
+               rt2800_bbp_write(rt2x00dev, 120, 0x50);
+
        if (rt2x00_rt(rt2x00dev, RT3290) ||
            rt2x00_rt(rt2x00dev, RT5390) ||
            rt2x00_rt(rt2x00dev, RT5392))
@@ -3466,6 +3647,9 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                rt2800_bbp_write(rt2x00dev, 135, 0xf6);
        }
 
+       if (rt2x00_rt(rt2x00dev, RT3352))
+               rt2800_bbp_write(rt2x00dev, 137, 0x0f);
+
        if (rt2x00_rt(rt2x00dev, RT3071) ||
            rt2x00_rt(rt2x00dev, RT3090) ||
            rt2x00_rt(rt2x00dev, RT3390) ||
@@ -3506,6 +3690,28 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                rt2800_bbp_write(rt2x00dev, 3, value);
        }
 
+       if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_bbp_write(rt2x00dev, 163, 0xbd);
+               /* Set ITxBF timeout to 0x9c40=1000msec */
+               rt2800_bbp_write(rt2x00dev, 179, 0x02);
+               rt2800_bbp_write(rt2x00dev, 180, 0x00);
+               rt2800_bbp_write(rt2x00dev, 182, 0x40);
+               rt2800_bbp_write(rt2x00dev, 180, 0x01);
+               rt2800_bbp_write(rt2x00dev, 182, 0x9c);
+               rt2800_bbp_write(rt2x00dev, 179, 0x00);
+               /* Reprogram the inband interface to put right values in RXWI */
+               rt2800_bbp_write(rt2x00dev, 142, 0x04);
+               rt2800_bbp_write(rt2x00dev, 143, 0x3b);
+               rt2800_bbp_write(rt2x00dev, 142, 0x06);
+               rt2800_bbp_write(rt2x00dev, 143, 0xa0);
+               rt2800_bbp_write(rt2x00dev, 142, 0x07);
+               rt2800_bbp_write(rt2x00dev, 143, 0xa1);
+               rt2800_bbp_write(rt2x00dev, 142, 0x08);
+               rt2800_bbp_write(rt2x00dev, 143, 0xa2);
+
+               rt2800_bbp_write(rt2x00dev, 148, 0xc8);
+       }
+
        if (rt2x00_rt(rt2x00dev, RT5390) ||
                rt2x00_rt(rt2x00dev, RT5392)) {
                int ant, div_mode;
@@ -3519,16 +3725,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
                        u32 reg;
 
-                       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
+                       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
                        if (ant == 0)
-                               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
+                               rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
                        else if (ant == 1)
-                               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
-                       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+                               rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
+                       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
                }
 
                /* This chip has hardware antenna diversity*/
@@ -3639,6 +3845,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
            !rt2x00_rt(rt2x00dev, RT3071) &&
            !rt2x00_rt(rt2x00dev, RT3090) &&
            !rt2x00_rt(rt2x00dev, RT3290) &&
+           !rt2x00_rt(rt2x00dev, RT3352) &&
            !rt2x00_rt(rt2x00dev, RT3390) &&
            !rt2x00_rt(rt2x00dev, RT3572) &&
            !rt2x00_rt(rt2x00dev, RT5390) &&
@@ -3835,6 +4042,70 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
                rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
                return 0;
+       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
+               rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
+               rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
+               rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
+               rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
+               rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
+               rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
+               rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
+               rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
+               rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
+               rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
+               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
+               rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
+               rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
+               rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
+               rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
+               rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
+               rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
+               rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
+               rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
+               rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
+               rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
+               rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
+               rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
+               rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
+               rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
+               rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
+               rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
+               rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
+               rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
+               rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
+               rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
+               rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
+               rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
+               rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
+               rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
+               rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
+               rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
+               rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
+               rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
+               rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
        } else if (rt2x00_rt(rt2x00dev, RT5390)) {
                rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
                rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
@@ -4021,6 +4292,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
                msleep(1);
                rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
+               rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
                rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
                rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
        }
@@ -4035,6 +4307,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                        rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
        } else if (rt2x00_rt(rt2x00dev, RT3071) ||
                   rt2x00_rt(rt2x00dev, RT3090) ||
+                  rt2x00_rt(rt2x00dev, RT3352) ||
                   rt2x00_rt(rt2x00dev, RT3390) ||
                   rt2x00_rt(rt2x00dev, RT3572)) {
                drv_data->calibration_bw20 =
@@ -4323,13 +4596,18 @@ void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 }
 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
 
-int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
+static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 {
        struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
        u16 word;
        u8 *mac;
        u8 default_lna_gain;
 
+       /*
+        * Read the EEPROM.
+        */
+       rt2800_read_eeprom(rt2x00dev);
+
        /*
         * Start validation of the data that has been read.
         */
@@ -4452,9 +4730,8 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
 
-int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
+static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
 {
        u32 reg;
        u16 value;
@@ -4493,6 +4770,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
        case RT3071:
        case RT3090:
        case RT3290:
+       case RT3352:
        case RT3390:
        case RT3572:
        case RT5390:
@@ -4515,6 +4793,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
        case RF3052:
        case RF3290:
        case RF3320:
+       case RF3322:
        case RF5360:
        case RF5370:
        case RF5372:
@@ -4539,6 +4818,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
 
        if (rt2x00_rt(rt2x00dev, RT3070) ||
            rt2x00_rt(rt2x00dev, RT3090) ||
+           rt2x00_rt(rt2x00dev, RT3352) ||
            rt2x00_rt(rt2x00dev, RT3390)) {
                value = rt2x00_get_field16(eeprom,
                                EEPROM_NIC_CONF1_ANT_DIVERSITY);
@@ -4612,7 +4892,6 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
 
 /*
  * RF value list for rt28xx
@@ -4755,7 +5034,7 @@ static const struct rf_channel rf_vals_3x[] = {
        {173, 0x61, 0, 9},
 };
 
-int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
+static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
 {
        struct hw_mode_spec *spec = &rt2x00dev->spec;
        struct channel_info *info;
@@ -4832,6 +5111,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
                   rt2x00_rf(rt2x00dev, RF3022) ||
                   rt2x00_rf(rt2x00dev, RF3290) ||
                   rt2x00_rf(rt2x00dev, RF3320) ||
+                  rt2x00_rf(rt2x00dev, RF3322) ||
                   rt2x00_rf(rt2x00dev, RF5360) ||
                   rt2x00_rf(rt2x00dev, RF5370) ||
                   rt2x00_rf(rt2x00dev, RF5372) ||
@@ -4931,7 +5211,72 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
+
+int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
+{
+       int retval;
+       u32 reg;
+
+       /*
+        * Allocate eeprom data.
+        */
+       retval = rt2800_validate_eeprom(rt2x00dev);
+       if (retval)
+               return retval;
+
+       retval = rt2800_init_eeprom(rt2x00dev);
+       if (retval)
+               return retval;
+
+       /*
+        * Enable rfkill polling by setting GPIO direction of the
+        * rfkill switch GPIO pin correctly.
+        */
+       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
+       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
+
+       /*
+        * Initialize hw specifications.
+        */
+       retval = rt2800_probe_hw_mode(rt2x00dev);
+       if (retval)
+               return retval;
+
+       /*
+        * Set device capabilities.
+        */
+       __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
+       __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
+       if (!rt2x00_is_usb(rt2x00dev))
+               __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
+
+       /*
+        * Set device requirements.
+        */
+       if (!rt2x00_is_soc(rt2x00dev))
+               __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
+       __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
+       __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
+       if (!rt2800_hwcrypt_disabled(rt2x00dev))
+               __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
+       __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
+       __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
+       if (rt2x00_is_usb(rt2x00dev))
+               __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
+       else {
+               __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
+               __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
+       }
+
+       /*
+        * Set the rssi offset.
+        */
+       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(rt2800_probe_hw);
 
 /*
  * IEEE80211 stack callback functions.