--- /dev/null
+//============================================================\r
+// Description:\r
+//\r
+// This file is for 8814A TXBF mechanism\r
+//\r
+//============================================================\r
+\r
+#include "mp_precomp.h"\r
+#include "../phydm_precomp.h"\r
+\r
+#if (BEAMFORMING_SUPPORT == 1)\r
+#if (RTL8814A_SUPPORT == 1)\r
+\r
+BOOLEAN\r
+phydm_beamforming_set_iqgen_8814A(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte i = 0;\r
+ u2Byte counter = 0;\r
+ u4Byte rf_mode[4];\r
+\r
+ for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/\r
+ }\r
+ \r
+ while(1) {\r
+ counter++;\r
+ for (i= ODM_RF_PATH_A; i < MAX_RF_PATH; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/\r
+ }\r
+\r
+ ODM_delay_us(2);\r
+ \r
+ for (i= ODM_RF_PATH_A; i < MAX_RF_PATH; i++) {\r
+ rf_mode[i] = ODM_GetRFReg(pDM_Odm, i, RF_RCK_OS, 0xfffff);\r
+ }\r
+ \r
+ if ((rf_mode[0] == 0x180000) && (rf_mode[1] == 0x180000) && (rf_mode[2] == 0x180000) && (rf_mode[3] == 0x180000))\r
+ break;\r
+ else if (counter == 100) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("iqgen setting fail:8814A \n"));\r
+ return FALSE;\r
+ }\r
+ }\r
+\r
+ for (i= ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/\r
+ ODM_SetRFReg(pDM_Odm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/\r
+ }\r
+ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/\r
+\r
+ for (i= ODM_RF_PATH_A; i < MAX_RF_PATH; i++) {\r
+ ODM_SetRFReg(pDM_Odm, i, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/\r
+ }\r
+\r
+ return TRUE;\r
+ \r
+}\r
+\r
+\r
+\r
+VOID\r
+HalTxbf8814A_setNDPArate(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte BW,\r
+ IN u1Byte Rate\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ \r
+ ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8814A, BW);\r
+ ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8814A, (u1Byte) Rate);\r
+\r
+}\r
+\r
+#define PHYDM_MEMORY_MAP_BUF_READ 0x8000\r
+#define PHYDM_CTRL_INFO_PAGE 0x660\r
+\r
+VOID\r
+phydm_DataRate_8814A(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN u1Byte macId, \r
+ OUT pu4Byte data,\r
+ IN u1Byte dataLen\r
+ )\r
+{\r
+ u1Byte i = 0;\r
+ u2Byte XReadDataAddr = 0;\r
+\r
+ ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);\r
+ XReadDataAddr = PHYDM_MEMORY_MAP_BUF_READ + macId*32; /*Ctrl Info: 32Bytes for each macid(n)*/\r
+ \r
+ if ((XReadDataAddr < PHYDM_MEMORY_MAP_BUF_READ) || (XReadDataAddr > 0x8FFF)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("XReadDataAddr(0x%x) is not correct!\n", XReadDataAddr));\r
+ return; \r
+ }\r
+ \r
+ /* Read data */\r
+ for (i = 0; i < dataLen; i++)\r
+ *(data+i) = ODM_Read2Byte(pDM_Odm, XReadDataAddr+i); \r
+ \r
+}\r
+\r
+VOID\r
+HalTxbf8814A_GetTxRate(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMEE_ENTRY pEntry;\r
+ u4Byte TxRptData = 0;\r
+ u1Byte DataRate = 0xFF;\r
+\r
+ pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]);\r
+ \r
+ phydm_DataRate_8814A(pDM_Odm, (u1Byte)pEntry->MacId, &TxRptData, 1);\r
+ DataRate = (u1Byte)TxRptData;\r
+ DataRate &= bMask7bits; /*Bit7 indicates SGI*/\r
+\r
+ pDM_Odm->TxBfDataRate = DataRate;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] pDM_Odm->TxBfDataRate = 0x%x\n", __func__, pDM_Odm->TxBfDataRate));\r
+}\r
+\r
+VOID\r
+HalTxbf8814A_ResetTxPath(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte idx\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+#if DEV_BUS_TYPE == RT_USB_INTERFACE\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ RT_BEAMFORMEE_ENTRY BeamformeeEntry;\r
+ u1Byte Nr_index = 0, txSS = 0;\r
+\r
+ if (idx < BEAMFORMEE_ENTRY_NUM)\r
+ BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx];\r
+ else\r
+ return;\r
+\r
+ if ((pDM_Odm->LastUSBHub) != (*pDM_Odm->HubUsbMode)) {\r
+ Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer);\r
+\r
+ if (*pDM_Odm->HubUsbMode == 2) {\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ txSS = 0xf;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ txSS = 0xe;\r
+ else\r
+ txSS = 0x6;\r
+ } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/\r
+ txSS = 0x6;\r
+ else\r
+ txSS = 0x6;\r
+\r
+ if (txSS == 0xf) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0);\r
+ } else if (txSS == 0xe) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0);\r
+ } else if (txSS == 0x6) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360);\r
+ }\r
+\r
+ if (idx == 0) {\r
+ switch (Nr_index) {\r
+ case 0:\r
+ break;\r
+\r
+ case 1: /*Nsts = 2 BC*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/\r
+ break;\r
+\r
+ case 2: /*Nsts = 3 BCD*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/\r
+ break;\r
+\r
+ default: /*Nr>3, same as Case 3*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/\r
+ break;\r
+ }\r
+ } else {\r
+ switch (Nr_index) {\r
+ case 0:\r
+ break;\r
+\r
+ case 1: /*Nsts = 2 BC*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/\r
+ break;\r
+\r
+ case 2: /*Nsts = 3 BCD*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/\r
+ break;\r
+\r
+ default: /*Nr>3, same as Case 3*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/\r
+ break;\r
+ }\r
+ }\r
+\r
+ pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode;\r
+ } else\r
+ return;\r
+#endif\r
+}\r
+\r
+\r
+u1Byte\r
+halTxbf8814A_GetNtx(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte Ntx = 0, txSS = 3;\r
+\r
+#if DEV_BUS_TYPE == RT_USB_INTERFACE\r
+ txSS = *pDM_Odm->HubUsbMode;\r
+#endif\r
+ if (txSS == 3 || txSS == 2) {\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ Ntx = 3;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ Ntx = 2;\r
+ else\r
+ Ntx = 1;\r
+ } else if (txSS == 1) /*USB 2.0 always 2Tx*/\r
+ Ntx = 1;\r
+ else\r
+ Ntx = 1;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx));\r
+ return Ntx;\r
+}\r
+\r
+u1Byte\r
+halTxbf8814A_GetNrx(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte Nrx = 0;\r
+\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ Nrx = 3;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ Nrx = 2;\r
+ else if (pDM_Odm->RFType == ODM_2T2R)\r
+ Nrx = 1;\r
+ else if (pDM_Odm->RFType == ODM_2T3R)\r
+ Nrx = 2;\r
+ else if (pDM_Odm->RFType == ODM_2T4R)\r
+ Nrx = 3;\r
+ else if (pDM_Odm->RFType == ODM_1T1R)\r
+ Nrx = 0;\r
+ else if (pDM_Odm->RFType == ODM_1T2R)\r
+ Nrx = 1;\r
+ else\r
+ Nrx = 0;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx));\r
+ return Nrx;\r
+}\r
+\r
+VOID\r
+halTxbf8814A_RfMode(\r
+ IN PVOID pDM_VOID,\r
+ IN PRT_BEAMFORMING_INFO pBeamformingInfo,\r
+ IN u1Byte idx\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte i, Nr_index = 0;\r
+ u1Byte txSS = 3; /*default use 3 Tx*/\r
+ RT_BEAMFORMEE_ENTRY BeamformeeEntry;\r
+\r
+ if (idx < BEAMFORMEE_ENTRY_NUM)\r
+ BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx];\r
+ else\r
+ return;\r
+\r
+ Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer);\r
+\r
+ if (pDM_Odm->RFType == ODM_1T1R)\r
+ return;\r
+\r
+ if (pBeamformingInfo->beamformee_su_cnt > 0) {\r
+#if DEV_BUS_TYPE == RT_USB_INTERFACE\r
+ pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode;\r
+ txSS = *pDM_Odm->HubUsbMode;\r
+#endif\r
+ if (txSS == 3 || txSS == 2) {\r
+ if (pDM_Odm->RFType == ODM_4T4R)\r
+ txSS = 0xf;\r
+ else if (pDM_Odm->RFType == ODM_3T3R)\r
+ txSS = 0xe;\r
+ else\r
+ txSS = 0x6;\r
+ } else if (txSS == 1) /*USB 2.0 always 2Tx*/\r
+ txSS = 0x6;\r
+ else\r
+ txSS = 0x6;\r
+\r
+ if (txSS == 0xf) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0);\r
+ } else if (txSS == 0xe) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0);\r
+ } else if (txSS == 0x6) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936);\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360);\r
+ }\r
+\r
+ /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT28 | BIT29, 0x2); /*enable BB TxBF ant mapping register*/\r
+ \r
+ if (idx == 0) {\r
+ switch (Nr_index) {\r
+ case 0:\r
+ break;\r
+\r
+ case 1: /*Nsts = 2 BC*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/\r
+ break;\r
+\r
+ case 2: /*Nsts = 3 BCD*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/\r
+ break;\r
+\r
+ default: /*Nr>3, same as Case 3*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/\r
+ \r
+ break;\r
+ }\r
+ } else {\r
+ switch (Nr_index) {\r
+ case 0:\r
+ break;\r
+\r
+ case 1: /*Nsts = 2 BC*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/\r
+ break;\r
+\r
+ case 2: /*Nsts = 3 BCD*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/\r
+ break;\r
+\r
+ default: /*Nr>3, same as Case 3*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if ((pBeamformingInfo->beamformee_su_cnt == 0) && (pBeamformingInfo->beamformer_su_cnt == 0)) {\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x932); /*set TxPath selection for 8814a BFer bug refine*/\r
+ ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e9360);\r
+ }\r
+}\r
+#if 0\r
+VOID\r
+halTxbf8814A_DownloadNDPA(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte u1bTmp = 0, tmpReg422 = 0;\r
+ u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;\r
+ u2Byte Head_Page = 0x7FE;\r
+ BOOLEAN bSendBeacon = FALSE;\r
+ u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/\r
+ PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;\r
+ PADAPTER Adapter = pDM_Odm->Adapter;\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;\r
+#endif\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));\r
+\r
+ Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy);\r
+\r
+ /*Set REG_CR bit 8. DMA beacon by SW.*/\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1);\r
+ ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp | BIT0));\r
+\r
+\r
+ /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\r
+ tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2);\r
+ ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6));\r
+\r
+ if (tmpReg422 & BIT6) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an Adapter is sending beacon.\n", __func__));\r
+ bSendBeacon = TRUE;\r
+ }\r
+\r
+ /*0x204[11:0] Beacon Head for TXDMA*/\r
+ ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, Head_Page);\r
+\r
+ do {\r
+ /*Clear beacon valid check bit.*/\r
+ BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1);\r
+ ODM_Write1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7));\r
+\r
+ /*download NDPA rsvd page.*/\r
+ if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)\r
+ Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE);\r
+ else\r
+ Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);\r
+\r
+ /*check rsvd page download OK.*/\r
+ BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1);\r
+ count = 0;\r
+ while (!(BcnValidReg & BIT7) && count < 20) {\r
+ count++;\r
+ ODM_delay_ms(10);\r
+ BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 2);\r
+ }\r
+ DLBcnCount++;\r
+ } while (!(BcnValidReg & BIT7) && DLBcnCount < 5);\r
+\r
+ if (!(BcnValidReg & BIT7))\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));\r
+\r
+ /*0x204[11:0] Beacon Head for TXDMA*/\r
+ ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy);\r
+\r
+ /*To make sure that if there exists an adapter which would like to send beacon.*/\r
+ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\r
+ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */\r
+ /*the beacon cannot be sent by HW.*/\r
+ /*2010.06.23. Added by tynli.*/\r
+ if (bSendBeacon)\r
+ ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422);\r
+\r
+ /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\r
+ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\r
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1);\r
+ ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp & (~BIT0)));\r
+\r
+ pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;\r
+#endif\r
+}\r
+\r
+VOID\r
+halTxbf8814A_FwTxBFCmd(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte Idx, Period = 0;\r
+ u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;\r
+ u1Byte u1TxBFParm[3] = {0};\r
+ PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;\r
+\r
+ for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {\r
+ if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\r
+ if (pBeamInfo->BeamformeeEntry[Idx].bSound) {\r
+ PageNum0 = 0xFE;\r
+ PageNum1 = 0x07;\r
+ Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);\r
+ } else if (PageNum0 == 0xFF) {\r
+ PageNum0 = 0xFF; /*stop sounding*/\r
+ PageNum1 = 0x0F;\r
+ }\r
+ }\r
+ }\r
+\r
+ u1TxBFParm[0] = PageNum0;\r
+ u1TxBFParm[1] = PageNum1;\r
+ u1TxBFParm[2] = Period;\r
+ ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, \r
+ ("[%s] PageNum0 = %d, PageNum1 = %d Period = %d\n", __func__, PageNum0, PageNum1, Period));\r
+}\r
+#endif\r
+VOID\r
+HalTxbf8814A_Enter(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte BFerBFeeIdx\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte i = 0;\r
+ u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;\r
+ u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ RT_BEAMFORMEE_ENTRY BeamformeeEntry;\r
+ RT_BEAMFORMER_ENTRY BeamformerEntry;\r
+ u2Byte STAid = 0, CSI_Param = 0;\r
+ u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerIdx, BFeeIdx));\r
+ ODM_SetMACReg(pDM_Odm, REG_SND_PTCL_CTRL_8814A, bMaskByte1 | bMaskByte2, 0x0202);\r
+\r
+ if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {\r
+ BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];\r
+ /*Sounding protocol control*/\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xDB);\r
+\r
+ /*MAC address/Partial AID of Beamformer*/\r
+ if (BFerIdx == 0) {\r
+ for (i = 0; i < 6 ; i++)\r
+ ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), BeamformerEntry.MacAddr[i]);\r
+ } else {\r
+ for (i = 0; i < 6 ; i++)\r
+ ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), BeamformerEntry.MacAddr[i]);\r
+ }\r
+\r
+ /*CSI report parameters of Beamformer*/\r
+ Nc_index = halTxbf8814A_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/\r
+ Nr_index = BeamformerEntry.NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/\r
+\r
+ grouping = 0;\r
+\r
+ /*for ac = 1, for n = 3*/\r
+ if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)\r
+ codebookinfo = 1;\r
+ else if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT)\r
+ codebookinfo = 3;\r
+\r
+ coefficientsize = 3;\r
+\r
+ CSI_Param = (u2Byte)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (Nr_index << 3) | (Nc_index));\r
+\r
+ if (BFerIdx == 0)\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, CSI_Param);\r
+ else\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, CSI_Param);\r
+ /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);\r
+\r
+ }\r
+\r
+ if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {\r
+ BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];\r
+\r
+ halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx);\r
+\r
+ if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))\r
+ STAid = BeamformeeEntry.MacId;\r
+ else\r
+ STAid = BeamformeeEntry.P_AID;\r
+\r
+ /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\r
+ if (BFeeIdx == 0) {\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, STAid);\r
+ ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7);\r
+ } else\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, STAid | BIT14 | BIT15 | BIT12);\r
+\r
+ /*CSI report parameters of Beamformee*/\r
+ if (BFeeIdx == 0) {\r
+ /*Get BIT24 & BIT25*/\r
+ u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;\r
+\r
+ ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, STAid | BIT9);\r
+ } else\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, STAid | 0xE200); /*Set BIT25*/\r
+\r
+ phydm_Beamforming_Notify(pDM_Odm);\r
+ }\r
+\r
+}\r
+\r
+\r
+VOID\r
+HalTxbf8814A_Leave(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ RT_BEAMFORMER_ENTRY BeamformerEntry;\r
+ RT_BEAMFORMEE_ENTRY BeamformeeEntry;\r
+\r
+ if (Idx < BEAMFORMER_ENTRY_NUM) {\r
+ BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];\r
+ BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];\r
+ } else\r
+ return;\r
+\r
+ /*Clear P_AID of Beamformee*/\r
+ /*Clear MAC address of Beamformer*/\r
+ /*Clear Associated Bfmee Sel*/\r
+\r
+ if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {\r
+ ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8);\r
+ if (Idx == 0) {\r
+ ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0);\r
+ } else {\r
+ ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);\r
+ ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);\r
+ }\r
+ }\r
+\r
+ if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {\r
+ halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx);\r
+ if (Idx == 0) {\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0);\r
+ ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7);\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);\r
+ } else {\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12);\r
+\r
+ ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);\r
+ }\r
+ }\r
+}\r
+\r
+VOID\r
+HalTxbf8814A_Status(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u2Byte BeamCtrlVal, tmpVal;\r
+ u4Byte BeamCtrlReg;\r
+ PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
+ RT_BEAMFORMEE_ENTRY BeamformEntry;\r
+\r
+ if (Idx < BEAMFORMEE_ENTRY_NUM)\r
+ BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx];\r
+ else\r
+ return;\r
+\r
+ if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))\r
+ BeamCtrlVal = BeamformEntry.MacId;\r
+ else\r
+ BeamCtrlVal = BeamformEntry.P_AID;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState));\r
+\r
+ if (Idx == 0)\r
+ BeamCtrlReg = REG_TXBF_CTRL_8814A;\r
+ else {\r
+ BeamCtrlReg = REG_TXBF_CTRL_8814A + 2;\r
+ BeamCtrlVal |= BIT12 | BIT14 | BIT15;\r
+ }\r
+\r
+ if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamformingInfo->applyVmatrix == TRUE)) {\r
+ if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)\r
+ BeamCtrlVal |= BIT9;\r
+ else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)\r
+ BeamCtrlVal |= (BIT9 | BIT10);\r
+ else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80)\r
+ BeamCtrlVal |= (BIT9 | BIT10 | BIT11);\r
+ } else {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__));\r
+ BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);\r
+ }\r
+\r
+ ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);\r
+ /*disable NDP packet use beamforming */\r
+ tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A);\r
+ ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15);\r
+\r
+}\r
+\r
+\r
+\r
+\r
+\r
+VOID\r
+HalTxbf8814A_FwTxBF(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte Idx\r
+)\r
+{\r
+#if 0\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;\r
+ PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));\r
+\r
+ if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)\r
+ halTxbf8814A_DownloadNDPA(pDM_Odm, Idx);\r
+\r
+ halTxbf8814A_FwTxBFCmd(pDM_Odm);\r
+#endif\r
+}\r
+\r
+#endif /* (RTL8814A_SUPPORT == 1)*/\r
+\r
+#endif\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff