net: wireless: rockchip: add rtl8822be pcie wifi driver

[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8822be / hal / phydm / rtl8822b / phydm_hal_api8822b.h

diff --git a/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/rtl8822b/phydm_hal_api8822b.h b/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/rtl8822b/phydm_hal_api8822b.h
new file mode 100644 (file)
index 0000000..bdf869e
--- /dev/null
+++ b/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/rtl8822b/phydm_hal_api8822b.h
@@ -0,0 +1,133 @@
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *                                        \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __INC_PHYDM_API_H_8822B__\r
+#define __INC_PHYDM_API_H_8822B__\r
+\r
+#if (RTL8822B_SUPPORT == 1)\r
+\r
+#define        PHY_CONFIG_VERSION_8822B                        "27.5.31"       /*2016.08.01     (HW user guide version: R27, SW user guide version: R05, Modification: R31)*/\r
+\r
+#define        INVALID_RF_DATA                                 0xffffffff\r
+#define        INVALID_TXAGC_DATA                              0xff\r
+\r
+#define        config_phydm_read_rf_check_8822b(data)                  (data != INVALID_RF_DATA)\r
+#define        config_phydm_read_txagc_check_8822b(data)               (data != INVALID_TXAGC_DATA)\r
+\r
+u4Byte\r
+config_phydm_read_rf_reg_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      ODM_RF_RADIO_PATH_E             RFPath,\r
+       IN      u4Byte                                  RegAddr,\r
+       IN      u4Byte                                  BitMask\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_write_rf_reg_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      ODM_RF_RADIO_PATH_E             RFPath,\r
+       IN      u4Byte                                  RegAddr,\r
+       IN      u4Byte                                  BitMask,\r
+       IN      u4Byte                                  Data\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_write_txagc_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      u4Byte                                  PowerIndex,\r
+       IN      ODM_RF_RADIO_PATH_E             Path,   \r
+       IN      u1Byte                                  HwRate\r
+       );\r
+\r
+u1Byte\r
+config_phydm_read_txagc_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      ODM_RF_RADIO_PATH_E             Path,\r
+       IN      u1Byte                                  HwRate\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_switch_band_8822b(        \r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      u1Byte                                  central_ch\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_switch_channel_8822b(     \r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      u1Byte                                  central_ch\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_switch_bandwidth_8822b(   \r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      u1Byte                                  primary_ch_idx,\r
+       IN      ODM_BW_E                                bandwidth\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_switch_channel_bw_8822b(  \r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      u1Byte                                  central_ch,\r
+       IN      u1Byte                                  primary_ch_idx,\r
+       IN      ODM_BW_E                                bandwidth\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_trx_mode_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      ODM_RF_PATH_E                   TxPath,\r
+       IN      ODM_RF_PATH_E                   RxPath,\r
+       IN      BOOLEAN                                 bTx2Path\r
+       );\r
+\r
+BOOLEAN\r
+config_phydm_parameter_init(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      ODM_PARAMETER_INIT_E    type\r
+       );\r
+\r
+\r
+/* ======================================================================== */\r
+/* These following functions can be used for PHY DM only*/\r
+\r
+BOOLEAN\r
+phydm_write_txagc_1byte_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm,\r
+       IN      u4Byte                                  PowerIndex,\r
+       IN      ODM_RF_RADIO_PATH_E             Path,   \r
+       IN      u1Byte                                  HwRate\r
+       );\r
+\r
+VOID\r
+phydm_init_hw_info_by_rfe_type_8822b(\r
+       IN      PDM_ODM_T                               pDM_Odm\r
+       );\r
+\r
+s4Byte\r
+phydm_get_condition_number_8822B(\r
+       IN      PDM_ODM_T                               pDM_Odm\r
+       );\r
+\r
+/* ======================================================================== */\r
+\r
+#endif /* RTL8822B_SUPPORT == 1 */\r
+#endif /*  __INC_PHYDM_API_H_8822B__ */\r
+\r
+\r