--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ \r
+#ifndef __ODM_REGDEFINE11N_H__\r
+#define __ODM_REGDEFINE11N_H__\r
+\r
+\r
+//2 RF REG LIST\r
+#define ODM_REG_RF_MODE_11N 0x00\r
+#define ODM_REG_RF_0B_11N 0x0B\r
+#define ODM_REG_CHNBW_11N 0x18\r
+#define ODM_REG_T_METER_11N 0x24\r
+#define ODM_REG_RF_25_11N 0x25\r
+#define ODM_REG_RF_26_11N 0x26\r
+#define ODM_REG_RF_27_11N 0x27\r
+#define ODM_REG_RF_2B_11N 0x2B\r
+#define ODM_REG_RF_2C_11N 0x2C\r
+#define ODM_REG_RXRF_A3_11N 0x3C\r
+#define ODM_REG_T_METER_92D_11N 0x42\r
+#define ODM_REG_T_METER_88E_11N 0x42\r
+\r
+\r
+\r
+//2 BB REG LIST\r
+//PAGE 8\r
+#define ODM_REG_BB_CTRL_11N 0x800\r
+#define ODM_REG_RF_PIN_11N 0x804\r
+#define ODM_REG_PSD_CTRL_11N 0x808\r
+#define ODM_REG_TX_ANT_CTRL_11N 0x80C\r
+#define ODM_REG_BB_PWR_SAV5_11N 0x818\r
+#define ODM_REG_CCK_RPT_FORMAT_11N 0x824\r
+#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C\r
+#define ODM_REG_RX_DEFUALT_A_11N 0x858\r
+#define ODM_REG_RX_DEFUALT_B_11N 0x85A\r
+#define ODM_REG_BB_PWR_SAV3_11N 0x85C\r
+#define ODM_REG_ANTSEL_CTRL_11N 0x860\r
+#define ODM_REG_RX_ANT_CTRL_11N 0x864\r
+#define ODM_REG_PIN_CTRL_11N 0x870\r
+#define ODM_REG_BB_PWR_SAV1_11N 0x874\r
+#define ODM_REG_ANTSEL_PATH_11N 0x878\r
+#define ODM_REG_BB_3WIRE_11N 0x88C\r
+#define ODM_REG_SC_CNT_11N 0x8C4\r
+#define ODM_REG_PSD_DATA_11N 0x8B4\r
+#define ODM_REG_CCX_PERIOD_11N 0x894\r
+#define ODM_REG_NHM_TH9_TH10_11N 0x890\r
+#define ODM_REG_CLM_11N 0x890\r
+#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898\r
+#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c\r
+#define ODM_REG_NHM_TH8_11N 0xe28\r
+#define ODM_REG_CLM_READY_11N 0x8b4\r
+#define ODM_REG_CLM_RESULT_11N 0x8d0\r
+#define ODM_REG_NHM_CNT_11N 0x8d8\r
+\r
+// For ACS, Jeffery, 2014-12-26\r
+#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc\r
+#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0\r
+#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4\r
+\r
+//PAGE 9\r
+#define ODM_REG_BB_CTRL_PAGE9_11N 0x900\r
+#define ODM_REG_DBG_RPT_11N 0x908\r
+#define ODM_REG_BB_TX_PATH_11N 0x90c\r
+#define ODM_REG_ANT_MAPPING1_11N 0x914\r
+#define ODM_REG_ANT_MAPPING2_11N 0x918\r
+#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948\r
+#define ODM_REG_RX_DFIR_MOD_97F 0x948\r
+\r
+//PAGE A\r
+#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00\r
+#define ODM_REG_CCK_ANT_SEL_11N 0xA04\r
+#define ODM_REG_CCK_CCA_11N 0xA0A\r
+#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C\r
+#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10\r
+#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14\r
+#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22\r
+#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23\r
+#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24\r
+#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25\r
+#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26\r
+#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27\r
+#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28\r
+#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29\r
+#define ODM_REG_CCK_FA_RST_11N 0xA2C\r
+#define ODM_REG_CCK_FA_MSB_11N 0xA58\r
+#define ODM_REG_CCK_FA_LSB_11N 0xA5C\r
+#define ODM_REG_CCK_CCA_CNT_11N 0xA60\r
+#define ODM_REG_BB_PWR_SAV4_11N 0xA74\r
+//PAGE B\r
+#define ODM_REG_LNA_SWITCH_11N 0xB2C\r
+#define ODM_REG_PATH_SWITCH_11N 0xB30\r
+#define ODM_REG_RSSI_CTRL_11N 0xB38\r
+#define ODM_REG_CONFIG_ANTA_11N 0xB68\r
+#define ODM_REG_RSSI_BT_11N 0xB9C\r
+#define ODM_REG_RXCK_RFMOD 0xBB0\r
+#define ODM_REG_EDCCA_DCNF_97F 0xBC0\r
+\r
+//PAGE C\r
+#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00\r
+#define ODM_REG_BB_RX_PATH_11N 0xC04\r
+#define ODM_REG_TRMUX_11N 0xC08\r
+#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C\r
+#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10\r
+#define ODM_REG_RXIQI_MATRIX_11N 0xC14\r
+#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C\r
+#define ODM_REG_IGI_A_11N 0xC50\r
+#define ODM_REG_ANTDIV_PARA2_11N 0xC54\r
+#define ODM_REG_IGI_B_11N 0xC58\r
+#define ODM_REG_ANTDIV_PARA3_11N 0xC5C\r
+#define ODM_REG_L1SBD_PD_CH_11N 0XC6C\r
+#define ODM_REG_BB_PWR_SAV2_11N 0xC70\r
+#define ODM_REG_BB_AGC_SET_2_11N 0xc74\r
+#define ODM_REG_RX_OFF_11N 0xC7C\r
+#define ODM_REG_TXIQK_MATRIXA_11N 0xC80\r
+#define ODM_REG_TXIQK_MATRIXB_11N 0xC88\r
+#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94\r
+#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C\r
+#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0\r
+#define ODM_REG_ANTDIV_PARA1_11N 0xCA4\r
+#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4\r
+#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0\r
+//PAGE D\r
+#define ODM_REG_OFDM_FA_RSTD_11N 0xD00\r
+#define ODM_REG_BB_RX_ANT_11N 0xD04\r
+#define ODM_REG_BB_ATC_11N 0xD2C\r
+#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0\r
+#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4\r
+#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8\r
+#define ODM_REG_RPT_11N 0xDF4\r
+//PAGE E\r
+#define ODM_REG_TXAGC_A_6_18_11N 0xE00\r
+#define ODM_REG_TXAGC_A_24_54_11N 0xE04\r
+#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08\r
+#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10\r
+#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14\r
+#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18\r
+#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C\r
+#define ODM_REG_EDCCA_DCNF_11N 0xE24\r
+#define ODM_REG_TAP_UPD_97F 0xE24\r
+#define ODM_REG_FPGA0_IQK_11N 0xE28\r
+#define ODM_REG_PAGE_B1_97F 0xE28\r
+#define ODM_REG_TXIQK_TONE_A_11N 0xE30\r
+#define ODM_REG_RXIQK_TONE_A_11N 0xE34\r
+#define ODM_REG_TXIQK_PI_A_11N 0xE38\r
+#define ODM_REG_RXIQK_PI_A_11N 0xE3C\r
+#define ODM_REG_TXIQK_11N 0xE40\r
+#define ODM_REG_RXIQK_11N 0xE44\r
+#define ODM_REG_IQK_AGC_PTS_11N 0xE48\r
+#define ODM_REG_IQK_AGC_RSP_11N 0xE4C\r
+#define ODM_REG_BLUETOOTH_11N 0xE6C\r
+#define ODM_REG_RX_WAIT_CCA_11N 0xE70\r
+#define ODM_REG_TX_CCK_RFON_11N 0xE74\r
+#define ODM_REG_TX_CCK_BBON_11N 0xE78\r
+#define ODM_REG_OFDM_RFON_11N 0xE7C\r
+#define ODM_REG_OFDM_BBON_11N 0xE80\r
+#define ODM_REG_TX2RX_11N 0xE84\r
+#define ODM_REG_TX2TX_11N 0xE88\r
+#define ODM_REG_RX_CCK_11N 0xE8C\r
+#define ODM_REG_RX_OFDM_11N 0xED0\r
+#define ODM_REG_RX_WAIT_RIFS_11N 0xED4\r
+#define ODM_REG_RX2RX_11N 0xED8\r
+#define ODM_REG_STANDBY_11N 0xEDC\r
+#define ODM_REG_SLEEP_11N 0xEE0\r
+#define ODM_REG_PMPD_ANAEN_11N 0xEEC\r
+/* PAGE F */\r
+#define ODM_REG_PAGE_F_RST_11N 0xF14\r
+#define ODM_REG_IGI_C_11N 0xF84\r
+#define ODM_REG_IGI_D_11N 0xF88\r
+#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84\r
+#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88\r
+#define ODM_REG_HT_CRC32_CNT_11N 0xF90\r
+#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94\r
+\r
+//2 MAC REG LIST\r
+#define ODM_REG_BB_RST_11N 0x02\r
+#define ODM_REG_ANTSEL_PIN_11N 0x4C\r
+#define ODM_REG_EARLY_MODE_11N 0x4D0\r
+#define ODM_REG_RSSI_MONITOR_11N 0x4FE\r
+#define ODM_REG_EDCA_VO_11N 0x500\r
+#define ODM_REG_EDCA_VI_11N 0x504\r
+#define ODM_REG_EDCA_BE_11N 0x508\r
+#define ODM_REG_EDCA_BK_11N 0x50C\r
+#define ODM_REG_TXPAUSE_11N 0x522\r
+#define ODM_REG_RESP_TX_11N 0x6D8\r
+#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0\r
+#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4\r
+\r
+\r
+//DIG Related\r
+#define ODM_BIT_IGI_11N 0x0000007F\r
+#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9\r
+#define ODM_BIT_BB_RX_PATH_11N 0xF\r
+#define ODM_BIT_BB_TX_PATH_11N 0xF\r
+#define ODM_BIT_BB_ATC_11N BIT11\r
+\r
+#endif\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff