--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+//============================================================\r
+// include files\r
+//============================================================\r
+#include "mp_precomp.h"\r
+#include "phydm_precomp.h"\r
+#include "phydm_noisemonitor.h"\r
+\r
+//=================================================\r
+// This function is for inband noise test utility only\r
+// To obtain the inband noise level(dbm), do the following.\r
+// 1. disable DIG and Power Saving \r
+// 2. Set initial gain = 0x1a\r
+// 3. Stop updating idle time pwer report (for driver read)\r
+// - 0x80c[25]\r
+//\r
+//=================================================\r
+\r
+#define Valid_Min -35\r
+#define Valid_Max 10\r
+#define ValidCnt 5 \r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+\r
+s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time)\r
+{\r
+ u4Byte tmp4b; \r
+ u1Byte max_rf_path=0,rf_path; \r
+ u1Byte reg_c50, reg_c58,valid_done=0; \r
+ struct noise_level noise_data;\r
+ u8Byte start = 0, func_start = 0, func_end = 0;\r
+\r
+ func_start = ODM_GetCurrentTime(pDM_Odm);\r
+ pDM_Odm->noise_level.noise_all = 0;\r
+ \r
+ if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) \r
+ max_rf_path = 2;\r
+ else\r
+ max_rf_path = 1;\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n"));\r
+\r
+ ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level));\r
+ \r
+ //\r
+ // Step 1. Disable DIG && Set initial gain.\r
+ //\r
+ \r
+ if(bPauseDIG)\r
+ {\r
+ odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue);\r
+ }\r
+ //\r
+ // Step 2. Disable all power save for read registers\r
+ //\r
+ //dcmd_DebugControlPowerSave(pAdapter, PSDisable);\r
+\r
+ //\r
+ // Step 3. Get noise power level\r
+ //\r
+ start = ODM_GetCurrentTime(pDM_Odm);\r
+ while(1)\r
+ {\r
+ \r
+ //Stop updating idle time pwer report (for driver read)\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1); \r
+ \r
+ //Read Noise Floor Report\r
+ tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord );\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));\r
+ \r
+ //ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain);\r
+ //if(max_rf_path == 2)\r
+ // ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain);\r
+ \r
+ //update idle time pwer report per 5us\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0);\r
+ \r
+ noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff); \r
+ noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8);\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n", \r
+ noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));\r
+\r
+ for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) \r
+ {\r
+ noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path];\r
+ noise_data.sval[rf_path] /= 2;\r
+ } \r
+ \r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n", \r
+ noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));\r
+ //ODM_delay_ms(10);\r
+ //ODM_sleep_ms(10);\r
+\r
+ for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) \r
+ {\r
+ if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min))\r
+ {\r
+ noise_data.valid_cnt[rf_path]++;\r
+ noise_data.sum[rf_path] += noise_data.sval[rf_path];\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path]));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path]));\r
+ if(noise_data.valid_cnt[rf_path] == ValidCnt)\r
+ { \r
+ valid_done++;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path]));\r
+ } \r
+ \r
+ }\r
+ \r
+ }\r
+\r
+ //printk("####### valid_done:%d #############\n",valid_done);\r
+ if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time))\r
+ {\r
+ for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)\r
+ { \r
+ //printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]);\r
+ if(noise_data.valid_cnt[rf_path])\r
+ noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; \r
+ else\r
+ noise_data.sum[rf_path] = 0;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+ reg_c50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);\r
+ reg_c50 &= ~BIT7;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));\r
+ pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (u1Byte)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);\r
+ pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];\r
+ \r
+ if(max_rf_path == 2){\r
+ reg_c58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);\r
+ reg_c58 &= ~BIT7;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));\r
+ pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (u1Byte)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);\r
+ pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];\r
+ }\r
+ pDM_Odm->noise_level.noise_all /= max_rf_path;\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n", \r
+ pDM_Odm->noise_level.noise[ODM_RF_PATH_A],\r
+ pDM_Odm->noise_level.noise[ODM_RF_PATH_B]));\r
+\r
+ //\r
+ // Step 4. Recover the Dig\r
+ //\r
+ if(bPauseDIG)\r
+ {\r
+ odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue);\r
+ } \r
+ func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ; \r
+ \r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));\r
+ return pDM_Odm->noise_level.noise_all;\r
+\r
+}\r
+\r
+s2Byte \r
+odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time\r
+ )\r
+{\r
+ s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/\r
+ s4Byte value32, pwdb_A = 0, sval, noise, sum;\r
+ BOOLEAN pd_flag;\r
+ u1Byte i, valid_cnt;\r
+ u8Byte start = 0, func_start = 0, func_end = 0;\r
+\r
+\r
+ if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))\r
+ return 0;\r
+ \r
+ func_start = ODM_GetCurrentTime(pDM_Odm);\r
+ pDM_Odm->noise_level.noise_all = 0;\r
+ \r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n"));\r
+ \r
+ /* Step 1. Disable DIG && Set initial gain. */\r
+ if (bPauseDIG)\r
+ odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue);\r
+\r
+ /* Step 2. Disable all power save for read registers */\r
+ /*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */\r
+\r
+ /* Step 3. Get noise power level */\r
+ start = ODM_GetCurrentTime(pDM_Odm);\r
+\r
+ /* reset counters */\r
+ sum = 0;\r
+ valid_cnt = 0;\r
+\r
+ /* Step 3. Get noise power level */\r
+ while (1) {\r
+ /*Set IGI=0x1C */\r
+ ODM_Write_DIG(pDM_Odm, 0x1C);\r
+ /*stop CK320&CK88 */\r
+ ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1);\r
+ /*Read Path-A */\r
+ ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/\r
+ value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/\r
+ \r
+ rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/\r
+ rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/\r
+\r
+ pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31);\r
+\r
+ /*Not in packet detection period or Tx state */\r
+ if ((!pd_flag) || (rxi_buf_anta != 0x200)) {\r
+ /*sign conversion*/\r
+ rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10);\r
+ rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10);\r
+\r
+ pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/\r
+\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF));\r
+ }\r
+ /*Start CK320&CK88*/\r
+ ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0);\r
+ /*BB Reset*/\r
+ ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0));\r
+ ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0);\r
+ /*PMAC Reset*/\r
+ ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) & (~BIT0));\r
+ ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) | BIT0);\r
+ /*CCK Reset*/\r
+ if (ODM_Read1Byte(pDM_Odm, 0x80B) & BIT4) {\r
+ ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) & (~BIT4));\r
+ ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) | BIT4); \r
+ }\r
+\r
+ sval = pwdb_A;\r
+\r
+ if (sval < 0 && sval >= -27) {\r
+ if (valid_cnt < ValidCnt) {\r
+ valid_cnt++;\r
+ sum += sval;\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum));\r
+ if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) {\r
+ sum /= valid_cnt;\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); \r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /*ADC backoff is 12dB,*/ \r
+ /*Ptarget=0x1C-110=-82dBm*/\r
+ noise = sum + 12 + 0x1C - 110; \r
+ \r
+ /*Offset*/\r
+ noise = noise - 3;\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise));\r
+ pDM_Odm->noise_level.noise_all = (s2Byte)noise;\r
+\r
+ /* Step 4. Recover the Dig*/\r
+ if (bPauseDIG)\r
+ odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue);\r
+ \r
+ func_end = ODM_GetProgressingTime(pDM_Odm, func_start);\r
+ \r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n"));\r
+\r
+ return pDM_Odm->noise_level.noise_all;\r
+}\r
+\r
+\r
+\r
+s2Byte\r
+ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time)\r
+{\r
+\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time);\r
+ else\r
+ return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time);\r
+}\r
+\r
+#endif\r
+\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff