--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ \r
+#ifndef __PHYDMDIG_H__\r
+#define __PHYDMDIG_H__\r
+\r
+#define DIG_VERSION "1.22" /* 2016.04.28 Stanley. Add CRC32 information in FA statistic */\r
+\r
+/* Pause DIG & CCKPD */\r
+#define DM_DIG_MAX_PAUSE_TYPE 0x7\r
+\r
+typedef enum tag_DIG_GoUpCheck_Level {\r
+\r
+ DIG_GOUPCHECK_LEVEL_0,\r
+ DIG_GOUPCHECK_LEVEL_1,\r
+ DIG_GOUPCHECK_LEVEL_2\r
+ \r
+} DIG_GOUPCHECK_LEVEL;\r
+\r
+typedef struct _Dynamic_Initial_Gain_Threshold_\r
+{\r
+ BOOLEAN bStopDIG; // for debug\r
+ BOOLEAN bIgnoreDIG;\r
+ BOOLEAN bPSDInProgress;\r
+\r
+ u1Byte Dig_Enable_Flag;\r
+ u1Byte Dig_Ext_Port_Stage;\r
+ \r
+ int RssiLowThresh;\r
+ int RssiHighThresh;\r
+\r
+ u4Byte FALowThresh;\r
+ u4Byte FAHighThresh;\r
+\r
+ u1Byte CurSTAConnectState;\r
+ u1Byte PreSTAConnectState;\r
+ u1Byte CurMultiSTAConnectState;\r
+\r
+ u1Byte PreIGValue;\r
+ u1Byte CurIGValue;\r
+ u1Byte BackupIGValue; //MP DIG\r
+ u1Byte BT30_CurIGI;\r
+ u1Byte IGIBackup;\r
+\r
+ s1Byte BackoffVal;\r
+ s1Byte BackoffVal_range_max;\r
+ s1Byte BackoffVal_range_min;\r
+ u1Byte rx_gain_range_max;\r
+ u1Byte rx_gain_range_min;\r
+ u1Byte Rssi_val_min;\r
+\r
+ u1Byte PreCCK_CCAThres;\r
+ u1Byte CurCCK_CCAThres;\r
+ u1Byte PreCCKPDState;\r
+ u1Byte CurCCKPDState;\r
+ u1Byte CCKPDBackup;\r
+ u1Byte pause_cckpd_level;\r
+ u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];\r
+\r
+ u1Byte LargeFAHit;\r
+ u1Byte LargeFA_Timeout; /*if (LargeFAHit), monitor "LargeFA_Timeout" sec, if timeout, LargeFAHit=0*/\r
+ u1Byte ForbiddenIGI;\r
+ u4Byte Recover_cnt;\r
+\r
+ u1Byte DIG_Dynamic_MIN_0;\r
+ u1Byte DIG_Dynamic_MIN_1;\r
+ BOOLEAN bMediaConnect_0;\r
+ BOOLEAN bMediaConnect_1;\r
+\r
+ u4Byte AntDiv_RSSI_max;\r
+ u4Byte RSSI_max;\r
+\r
+ u1Byte *bP2PInProcess;\r
+\r
+ u1Byte pause_dig_level;\r
+ u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];\r
+\r
+ u4Byte cckFaMa;\r
+ DIG_GOUPCHECK_LEVEL DIG_GoUpCheck_Level;\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+ BOOLEAN bTpTarget;\r
+ BOOLEAN bNoiseEst;\r
+ u4Byte TpTrainTH_min;\r
+ u1Byte IGIOffset_A;\r
+ u1Byte IGIOffset_B;\r
+#endif\r
+\r
+#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)\r
+ u1Byte rfGainIdx;\r
+ u1Byte agcTableIdx;\r
+ u1Byte bigJumpLmt[16];\r
+ u1Byte enableAdjustBigJump:1;\r
+ u1Byte bigJumpStep1:3;\r
+ u1Byte bigJumpStep2:2;\r
+ u1Byte bigJumpStep3:2;\r
+#endif\r
+}DIG_T,*pDIG_T;\r
+\r
+typedef struct _FALSE_ALARM_STATISTICS{\r
+ u4Byte Cnt_Parity_Fail;\r
+ u4Byte Cnt_Rate_Illegal;\r
+ u4Byte Cnt_Crc8_fail;\r
+ u4Byte Cnt_Mcs_fail;\r
+ u4Byte Cnt_Ofdm_fail;\r
+ u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A\r
+ u4Byte Cnt_Cck_fail;\r
+ u4Byte Cnt_all;\r
+ u4Byte Cnt_all_pre;\r
+ u4Byte Cnt_Fast_Fsync;\r
+ u4Byte Cnt_SB_Search_fail;\r
+ u4Byte Cnt_OFDM_CCA;\r
+ u4Byte Cnt_CCK_CCA;\r
+ u4Byte Cnt_CCA_all;\r
+ u4Byte Cnt_BW_USC; //Gary\r
+ u4Byte Cnt_BW_LSC; //Gary\r
+ u4Byte cnt_cck_crc32_error;\r
+ u4Byte cnt_cck_crc32_ok;\r
+ u4Byte cnt_ofdm_crc32_error;\r
+ u4Byte cnt_ofdm_crc32_ok;\r
+ u4Byte cnt_ht_crc32_error;\r
+ u4Byte cnt_ht_crc32_ok;\r
+ u4Byte cnt_vht_crc32_error;\r
+ u4Byte cnt_vht_crc32_ok;\r
+ u4Byte cnt_crc32_error_all;\r
+ u4Byte cnt_crc32_ok_all;\r
+ BOOLEAN cck_block_enable;\r
+ BOOLEAN ofdm_block_enable;\r
+ u4Byte dbg_port0;\r
+ BOOLEAN edcca_flag;\r
+}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;\r
+\r
+typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition\r
+{\r
+ DIG_TYPE_THRESH_HIGH = 0,\r
+ DIG_TYPE_THRESH_LOW = 1,\r
+ DIG_TYPE_BACKOFF = 2,\r
+ DIG_TYPE_RX_GAIN_MIN = 3,\r
+ DIG_TYPE_RX_GAIN_MAX = 4,\r
+ DIG_TYPE_ENABLE = 5,\r
+ DIG_TYPE_DISABLE = 6, \r
+ DIG_OP_TYPE_MAX\r
+}DM_DIG_OP_E;\r
+\r
+/*\r
+typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition\r
+{\r
+ CCK_PD_STAGE_LowRssi = 0,\r
+ CCK_PD_STAGE_HighRssi = 1,\r
+ CCK_PD_STAGE_MAX = 3,\r
+}DM_CCK_PDTH_E;\r
+\r
+typedef enum tag_DIG_EXT_PORT_ALGO_Definition\r
+{\r
+ DIG_EXT_PORT_STAGE_0 = 0,\r
+ DIG_EXT_PORT_STAGE_1 = 1,\r
+ DIG_EXT_PORT_STAGE_2 = 2,\r
+ DIG_EXT_PORT_STAGE_3 = 3,\r
+ DIG_EXT_PORT_STAGE_MAX = 4,\r
+}DM_DIG_EXT_PORT_ALG_E;\r
+\r
+typedef enum tag_DIG_Connect_Definition\r
+{\r
+ DIG_STA_DISCONNECT = 0, \r
+ DIG_STA_CONNECT = 1,\r
+ DIG_STA_BEFORE_CONNECT = 2,\r
+ DIG_MultiSTA_DISCONNECT = 3,\r
+ DIG_MultiSTA_CONNECT = 4,\r
+ DIG_CONNECT_MAX\r
+}DM_DIG_CONNECT_E;\r
+\r
+\r
+#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}\r
+\r
+#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \\r
+ DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)\r
+\r
+#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \\r
+ DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)\r
+*/\r
+\r
+typedef enum tag_PHYDM_Pause_Type {\r
+ PHYDM_PAUSE = BIT0,\r
+ PHYDM_RESUME = BIT1\r
+} PHYDM_PAUSE_TYPE;\r
+\r
+typedef enum tag_PHYDM_Pause_Level {\r
+/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */\r
+ PHYDM_PAUSE_LEVEL_0 = 0,\r
+ PHYDM_PAUSE_LEVEL_1 = 1,\r
+ PHYDM_PAUSE_LEVEL_2 = 2,\r
+ PHYDM_PAUSE_LEVEL_3 = 3,\r
+ PHYDM_PAUSE_LEVEL_4 = 4,\r
+ PHYDM_PAUSE_LEVEL_5 = 5,\r
+ PHYDM_PAUSE_LEVEL_6 = 6,\r
+ PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */\r
+} PHYDM_PAUSE_LEVEL;\r
+\r
+#define DM_DIG_THRESH_HIGH 40\r
+#define DM_DIG_THRESH_LOW 35\r
+\r
+#define DM_FALSEALARM_THRESH_LOW 400\r
+#define DM_FALSEALARM_THRESH_HIGH 1000\r
+\r
+#define DM_DIG_MAX_NIC 0x3e\r
+#define DM_DIG_MIN_NIC 0x20\r
+#define DM_DIG_MAX_OF_MIN_NIC 0x3e\r
+\r
+#define DM_DIG_MAX_AP 0x3e\r
+#define DM_DIG_MIN_AP 0x20\r
+#define DM_DIG_MAX_OF_MIN 0x2A //0x32\r
+#define DM_DIG_MIN_AP_DFS 0x20\r
+\r
+#define DM_DIG_MAX_NIC_HP 0x46\r
+#define DM_DIG_MIN_NIC_HP 0x2e\r
+\r
+#define DM_DIG_MAX_AP_HP 0x42\r
+#define DM_DIG_MIN_AP_HP 0x30\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+#define DM_DIG_MAX_AP_COVERAGR 0x26\r
+#define DM_DIG_MIN_AP_COVERAGE 0x1c\r
+#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22\r
+\r
+#define DM_DIG_TP_Target_TH0 500\r
+#define DM_DIG_TP_Target_TH1 1000\r
+#define DM_DIG_TP_Training_Period 10\r
+#endif\r
+\r
+//vivi 92c&92d has different definition, 20110504\r
+//this is for 92c\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE)\r
+ #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV\r
+ #define DM_DIG_FA_TH0 0x80//0x20\r
+ #else\r
+ #define DM_DIG_FA_TH0 0x200//0x20\r
+ #endif\r
+#else\r
+ #define DM_DIG_FA_TH0 0x200//0x20\r
+#endif\r
+\r
+#define DM_DIG_FA_TH1 0x300\r
+#define DM_DIG_FA_TH2 0x400\r
+//this is for 92d\r
+#define DM_DIG_FA_TH0_92D 0x100\r
+#define DM_DIG_FA_TH1_92D 0x400\r
+#define DM_DIG_FA_TH2_92D 0x600\r
+\r
+#define DM_DIG_BACKOFF_MAX 12\r
+#define DM_DIG_BACKOFF_MIN -4\r
+#define DM_DIG_BACKOFF_DEFAULT 10\r
+\r
+#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps\r
+#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps\r
+#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps\r
+#define RSSI_OFFSET_DIG 0x05\r
+#define LARGE_FA_TIMEOUT 60\r
+\r
+\r
+VOID\r
+ODM_ChangeDynamicInitGainThresh(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte DM_Type,\r
+ IN u4Byte DM_Value\r
+ );\r
+\r
+VOID\r
+ODM_Write_DIG(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte CurrentIGI\r
+ );\r
+\r
+VOID\r
+odm_PauseDIG(\r
+ IN PVOID pDM_VOID,\r
+ IN PHYDM_PAUSE_TYPE PauseType,\r
+ IN PHYDM_PAUSE_LEVEL pause_level,\r
+ IN u1Byte IGIValue\r
+ );\r
+\r
+VOID\r
+odm_DIGInit(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID \r
+odm_DIG(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+odm_DIGbyRSSI_LPS(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID \r
+odm_FalseAlarmCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+odm_PauseCCKPacketDetection(\r
+ IN PVOID pDM_VOID,\r
+ IN PHYDM_PAUSE_TYPE PauseType,\r
+ IN PHYDM_PAUSE_LEVEL pause_level,\r
+ IN u1Byte CCKPDThreshold\r
+ );\r
+\r
+VOID \r
+odm_CCKPacketDetectionThresh(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID \r
+ODM_Write_CCK_CCA_Thres(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte CurCCK_CCAThres\r
+ );\r
+\r
+BOOLEAN\r
+phydm_DIG_GoUpCheck(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+VOID\r
+odm_MPT_DIGCallback(\r
+ PRT_TIMER pTimer\r
+);\r
+\r
+VOID\r
+odm_MPT_DIGWorkItemCallback(\r
+ IN PVOID pContext\r
+ );\r
+\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+VOID\r
+odm_MPT_DIGCallback(\r
+ IN PVOID pDM_VOID\r
+);\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE != ODM_CE)\r
+VOID\r
+ODM_MPT_DIG(\r
+ IN PVOID pDM_VOID\r
+);\r
+#endif\r
+\r
+\r
+#endif\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff