--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __HALDMOUTSRC_H__\r
+#define __HALDMOUTSRC_H__\r
+\r
+//============================================================\r
+// include files\r
+//============================================================\r
+#include "phydm_pre_define.h"\r
+#include "phydm_dig.h"\r
+#include "phydm_edcaturbocheck.h"\r
+#include "phydm_pathdiv.h"\r
+#include "phydm_antdiv.h"\r
+#include "phydm_antdect.h"\r
+#include "phydm_dynamicbbpowersaving.h"\r
+#include "phydm_rainfo.h"\r
+#include "phydm_dynamictxpower.h"\r
+#include "phydm_cfotracking.h"\r
+#include "phydm_acs.h"\r
+#include "phydm_adaptivity.h"\r
+#include "phydm_iqk.h"\r
+#include "phydm_dfs.h"\r
+#include "phydm_ccx.h"\r
+#include "txbf/phydm_hal_txbf_api.h"\r
+\r
+#include "phydm_adc_sampling.h"\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+#include "phydm_beamforming.h"\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+#include "halphyrf_ap.h"\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
+#include "phydm_noisemonitor.h"\r
+#include "halphyrf_ce.h"\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) \r
+#include "halphyrf_win.h"\r
+#include "phydm_noisemonitor.h"\r
+#endif\r
+\r
+//============================================================\r
+// Definition \r
+//============================================================\r
+//\r
+// 2011/09/22 MH Define all team supprt ability.\r
+//\r
+\r
+/* Traffic load decision */\r
+#define TRAFFIC_ULTRA_LOW 1\r
+#define TRAFFIC_LOW 2\r
+#define TRAFFIC_MID 3\r
+#define TRAFFIC_HIGH 4\r
+\r
+#define NONE 0\r
+\r
+/*NBI API------------------------------------*/\r
+#define NBI_ENABLE 1\r
+#define NBI_DISABLE 2\r
+\r
+#define NBI_TABLE_SIZE_128 27\r
+#define NBI_TABLE_SIZE_256 59\r
+\r
+#define NUM_START_CH_80M 7\r
+#define NUM_START_CH_40M 14\r
+\r
+#define CH_OFFSET_40M 2\r
+#define CH_OFFSET_80M 6\r
+\r
+/*CSI MASK API------------------------------------*/\r
+#define CSI_MASK_ENABLE 1\r
+#define CSI_MASK_DISABLE 2\r
+\r
+/*------------------------------------------------*/\r
+\r
+#define FFT_128_TYPE 1\r
+#define FFT_256_TYPE 2\r
+\r
+#define SET_SUCCESS 1\r
+#define SET_ERROR 2\r
+#define SET_NO_NEED 3\r
+\r
+#define FREQ_POSITIVE 1\r
+#define FREQ_NEGATIVE 2\r
+\r
+\r
+\r
+//============================================================\r
+// structure and define\r
+//============================================================\r
+\r
+//\r
+// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.\r
+// We need to remove to other position???\r
+//\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+typedef struct rtl8192cd_priv {\r
+ u1Byte temp;\r
+\r
+}rtl8192cd_priv, *prtl8192cd_priv;\r
+#endif\r
+\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
+typedef struct _ADAPTER{\r
+ u1Byte temp;\r
+ #ifdef AP_BUILD_WORKAROUND\r
+ HAL_DATA_TYPE* temp2;\r
+ prtl8192cd_priv priv;\r
+ #endif\r
+}ADAPTER, *PADAPTER;\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+\r
+typedef struct _WLAN_STA{\r
+ u1Byte temp;\r
+} WLAN_STA, *PRT_WLAN_STA;\r
+\r
+#endif\r
+\r
+typedef struct _Dynamic_Primary_CCA{\r
+ u1Byte PriCCA_flag;\r
+ u1Byte intf_flag;\r
+ u1Byte intf_type; \r
+ u1Byte DupRTS_flag;\r
+ u1Byte Monitor_flag;\r
+ u1Byte CH_offset;\r
+ u1Byte MF_state;\r
+}Pri_CCA_T, *pPri_CCA_T;\r
+\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
+ #ifdef ADSL_AP_BUILD_WORKAROUND\r
+ #define MAX_TOLERANCE 5\r
+ #define IQK_DELAY_TIME 1 /*ms*/\r
+ #endif\r
+#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/\r
+\r
+#define DM_Type_ByFW 0\r
+#define DM_Type_ByDriver 1\r
+\r
+//\r
+// Declare for common info\r
+//\r
+\r
+#define IQK_THRESHOLD 8\r
+#define DPK_THRESHOLD 4\r
+\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+__PACK typedef struct _ODM_Phy_Status_Info_\r
+{\r
+ u1Byte RxPWDBAll;\r
+ u1Byte SignalQuality; /* in 0-100 index. */\r
+ u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */\r
+ s1Byte RxMIMOSignalQuality[4]; /* EVM */\r
+ s1Byte RxSNR[4]; /* per-path's SNR */\r
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\r
+ u1Byte RxCount:2; /* RX path counter---*/\r
+ u1Byte BandWidth:2;\r
+ u1Byte rxsc:4; /* sub-channel---*/\r
+#else\r
+ u1Byte BandWidth;\r
+#endif\r
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\r
+ u1Byte channel; /* channel number---*/\r
+ BOOLEAN bMuPacket; /* is MU packet or not---*/\r
+ BOOLEAN bBeamformed; /* BF packet---*/\r
+#endif\r
+} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T;\r
+\r
+typedef struct _ODM_Phy_Status_Info_Append_\r
+{\r
+ u1Byte MAC_CRC32; \r
+\r
+}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T;\r
+\r
+#else\r
+\r
+typedef struct _ODM_Phy_Status_Info_\r
+{\r
+ //\r
+ // Be care, if you want to add any element please insert between \r
+ // RxPWDBAll & SignalStrength.\r
+ //\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
+ u4Byte RxPWDBAll; \r
+#else\r
+ u1Byte RxPWDBAll; \r
+#endif\r
+ u1Byte SignalQuality; /* in 0-100 index. */\r
+ s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */\r
+ u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */\r
+ u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */\r
+ s2Byte Cfo_short[4]; /* per-path's Cfo_short */\r
+ s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */\r
+ s1Byte RxPower; /* in dBm Translate from PWdB */\r
+ s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */\r
+ u1Byte BTRxRSSIPercentage;\r
+ u1Byte SignalStrength; /* in 0-100 index. */\r
+ s1Byte RxPwr[4]; /* per-path's pwdb */\r
+ s1Byte RxSNR[4]; /* per-path's SNR */\r
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\r
+ u1Byte RxCount:2; /* RX path counter---*/\r
+ u1Byte BandWidth:2;\r
+ u1Byte rxsc:4; /* sub-channel---*/\r
+#else\r
+ u1Byte BandWidth;\r
+#endif\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
+ u1Byte btCoexPwrAdjust;\r
+#endif\r
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\r
+ u1Byte channel; /* channel number---*/\r
+ BOOLEAN bMuPacket; /* is MU packet or not---*/\r
+ BOOLEAN bBeamformed; /* BF packet---*/\r
+#endif\r
+}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;\r
+#endif\r
+\r
+typedef struct _ODM_Per_Pkt_Info_\r
+{\r
+ //u1Byte Rate; \r
+ u1Byte DataRate;\r
+ u1Byte StationID;\r
+ BOOLEAN bPacketMatchBSSID;\r
+ BOOLEAN bPacketToSelf;\r
+ BOOLEAN bPacketBeacon;\r
+ BOOLEAN bToSelf;\r
+}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;\r
+\r
+\r
+typedef struct _ODM_Phy_Dbg_Info_\r
+{\r
+ //ODM Write,debug info\r
+ s1Byte RxSNRdB[4];\r
+ u4Byte NumQryPhyStatus;\r
+ u4Byte NumQryPhyStatusCCK;\r
+ u4Byte NumQryPhyStatusOFDM;\r
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\r
+ u4Byte NumQryMuPkt;\r
+ u4Byte NumQryBfPkt;\r
+ u4Byte NumQryMuVhtPkt[40];\r
+ u4Byte NumQryVhtPkt[40];\r
+#endif\r
+ u1Byte NumQryBeaconPkt;\r
+ //Others\r
+ s4Byte RxEVM[4]; \r
+ \r
+}ODM_PHY_DBG_INFO_T;\r
+\r
+\r
+typedef struct _ODM_Mac_Status_Info_\r
+{\r
+ u1Byte test;\r
+ \r
+}ODM_MAC_INFO;\r
+\r
+//\r
+// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T\r
+// Please declare below ODM relative info in your STA info structure.\r
+//\r
+#if 1\r
+typedef struct _ODM_STA_INFO{\r
+ // Driver Write\r
+ BOOLEAN bUsed; // record the sta status link or not?\r
+ //u1Byte WirelessMode; // \r
+ u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E\r
+\r
+ // ODM Write\r
+ //1 PHY_STATUS_INFO\r
+ u1Byte RSSI_Path[4]; // \r
+ u1Byte RSSI_Ave;\r
+ u1Byte RXEVM[4];\r
+ u1Byte RXSNR[4];\r
+\r
+ // ODM Write\r
+ //1 TX_INFO (may changed by IC)\r
+ //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer.\r
+#if 0\r
+ u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit\r
+ u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit\r
+ u1Byte ANTSEL_C; //only in Jagar: 4bit\r
+ u1Byte ANTSEL_D; //only in Jagar: 4bit\r
+ u1Byte TX_ANTL; //not in Jagar: 2bit\r
+ u1Byte TX_ANT_HT; //not in Jagar: 2bit\r
+ u1Byte TX_ANT_CCK; //not in Jagar: 2bit\r
+ u1Byte TXAGC_A; //not in Jagar: 4bit\r
+ u1Byte TXAGC_B; //not in Jagar: 4bit\r
+ u1Byte TXPWR_OFFSET; //only in Jagar: 3bit\r
+ u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK\r
+#endif\r
+\r
+ //\r
+ // Please use compile flag to disabe the strcutrue for other IC except 88E.\r
+ // Move To lower layer.\r
+ //\r
+ // ODM Write Wilson will handle this part(said by Luke.Lee)\r
+ //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer.\r
+#if 0 \r
+ //1 For 88E RA (don't redefine the naming)\r
+ u1Byte rate_id;\r
+ u1Byte rate_SGI;\r
+ u1Byte rssi_sta_ra;\r
+ u1Byte SGI_enable;\r
+ u1Byte Decision_rate;\r
+ u1Byte Pre_rate;\r
+ u1Byte Active;\r
+\r
+ // Driver write Wilson handle.\r
+ //1 TX_RPT (don't redefine the naming)\r
+ u2Byte RTY[4]; // ???\r
+ u2Byte TOTAL; // ???\r
+ u2Byte DROP; // ???\r
+ //\r
+ // Please use compile flag to disabe the strcutrue for other IC except 88E.\r
+ //\r
+#endif\r
+\r
+}ODM_STA_INFO_T, *PODM_STA_INFO_T;\r
+#endif\r
+\r
+//\r
+// 2011/10/20 MH Define Common info enum for all team.\r
+//\r
+typedef enum _ODM_Common_Info_Definition\r
+{\r
+//-------------REMOVED CASE-----------//\r
+ //ODM_CMNINFO_CCK_HP,\r
+ //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? \r
+ //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E\r
+ //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E\r
+//-------------REMOVED CASE-----------//\r
+\r
+ //\r
+ // Fixed value:\r
+ //\r
+\r
+ //-----------HOOK BEFORE REG INIT-----------//\r
+ ODM_CMNINFO_PLATFORM = 0,\r
+ ODM_CMNINFO_ABILITY, // ODM_ABILITY_E\r
+ ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E\r
+ ODM_CMNINFO_MP_TEST_CHIP,\r
+ ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E\r
+ ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E\r
+ ODM_CMNINFO_FAB_VER, // ODM_FAB_E\r
+ ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E?\r
+ ODM_CMNINFO_RFE_TYPE, \r
+ ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E\r
+ ODM_CMNINFO_PACKAGE_TYPE,\r
+ ODM_CMNINFO_EXT_LNA, // TRUE\r
+ ODM_CMNINFO_5G_EXT_LNA, \r
+ ODM_CMNINFO_EXT_PA,\r
+ ODM_CMNINFO_5G_EXT_PA,\r
+ ODM_CMNINFO_GPA,\r
+ ODM_CMNINFO_APA,\r
+ ODM_CMNINFO_GLNA,\r
+ ODM_CMNINFO_ALNA,\r
+ ODM_CMNINFO_EXT_TRSW,\r
+ ODM_CMNINFO_EXT_LNA_GAIN,\r
+ ODM_CMNINFO_PATCH_ID, //CUSTOMER ID\r
+ ODM_CMNINFO_BINHCT_TEST,\r
+ ODM_CMNINFO_BWIFI_TEST,\r
+ ODM_CMNINFO_SMART_CONCURRENT,\r
+ ODM_CMNINFO_CONFIG_BB_RF,\r
+ ODM_CMNINFO_DOMAIN_CODE_2G,\r
+ ODM_CMNINFO_DOMAIN_CODE_5G,\r
+ ODM_CMNINFO_IQKFWOFFLOAD,\r
+ ODM_CMNINFO_IQKPAOFF,\r
+ ODM_CMNINFO_HUBUSBMODE,\r
+ ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,\r
+ ODM_CMNINFO_TX_TP,\r
+ ODM_CMNINFO_RX_TP,\r
+ ODM_CMNINFO_SOUNDING_SEQ,\r
+ ODM_CMNINFO_REGRFKFREEENABLE,\r
+ ODM_CMNINFO_RFKFREEENABLE,\r
+ ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,\r
+ /*-----------HOOK BEFORE REG INIT-----------*/\r
+\r
+\r
+ //\r
+ // Dynamic value:\r
+ //\r
+//--------- POINTER REFERENCE-----------//\r
+ ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E\r
+ ODM_CMNINFO_TX_UNI,\r
+ ODM_CMNINFO_RX_UNI,\r
+ ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E\r
+ ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E\r
+ ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E\r
+ ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E\r
+ ODM_CMNINFO_BW, // ODM_BW_E\r
+ ODM_CMNINFO_CHNL,\r
+ ODM_CMNINFO_FORCED_RATE,\r
+ \r
+ ODM_CMNINFO_DMSP_GET_VALUE,\r
+ ODM_CMNINFO_BUDDY_ADAPTOR,\r
+ ODM_CMNINFO_DMSP_IS_MASTER,\r
+ ODM_CMNINFO_SCAN,\r
+ ODM_CMNINFO_POWER_SAVING,\r
+ ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E\r
+ ODM_CMNINFO_DRV_STOP,\r
+ ODM_CMNINFO_PNP_IN,\r
+ ODM_CMNINFO_INIT_ON,\r
+ ODM_CMNINFO_ANT_TEST,\r
+ ODM_CMNINFO_NET_CLOSED,\r
+ //ODM_CMNINFO_RTSTA_AID, // For win driver only?\r
+ ODM_CMNINFO_FORCED_IGI_LB,\r
+ ODM_CMNINFO_P2P_LINK,\r
+ ODM_CMNINFO_FCS_MODE,\r
+ ODM_CMNINFO_IS1ANTENNA,\r
+ ODM_CMNINFO_RFDEFAULTPATH,\r
+ ODM_CMNINFO_DFS_MASTER_ENABLE,\r
+ ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,\r
+//--------- POINTER REFERENCE-----------//\r
+\r
+//------------CALL BY VALUE-------------//\r
+ ODM_CMNINFO_WIFI_DIRECT,\r
+ ODM_CMNINFO_WIFI_DISPLAY,\r
+ ODM_CMNINFO_LINK_IN_PROGRESS, \r
+ ODM_CMNINFO_LINK,\r
+ ODM_CMNINFO_STATION_STATE,\r
+ ODM_CMNINFO_RSSI_MIN,\r
+ ODM_CMNINFO_DBG_COMP, /* u4SByte*/\r
+ ODM_CMNINFO_DBG_LEVEL, /* u4Byte*/\r
+ ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u1Byte*/\r
+ ODM_CMNINFO_RA_THRESHOLD_LOW, /* u1Byte*/\r
+ ODM_CMNINFO_RF_ANTENNA_TYPE, /* u1Byte*/\r
+ ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,\r
+ ODM_CMNINFO_BE_FIX_TX_ANT,\r
+ ODM_CMNINFO_BT_ENABLED,\r
+ ODM_CMNINFO_BT_HS_CONNECT_PROCESS,\r
+ ODM_CMNINFO_BT_HS_RSSI,\r
+ ODM_CMNINFO_BT_OPERATION,\r
+ ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not\r
+ ODM_CMNINFO_BT_DIG,\r
+ ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil \r
+ ODM_CMNINFO_BT_DISABLE_EDCA,\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23\r
+#ifdef UNIVERSAL_REPEATER\r
+ ODM_CMNINFO_VXD_LINK,\r
+#endif\r
+#endif\r
+ ODM_CMNINFO_AP_TOTAL_NUM,\r
+ ODM_CMNINFO_POWER_TRAINING,\r
+ ODM_CMNINFO_DFS_REGION_DOMAIN,\r
+//------------CALL BY VALUE-------------//\r
+\r
+ //\r
+ // Dynamic ptr array hook itms.\r
+ //\r
+ ODM_CMNINFO_STA_STATUS,\r
+ ODM_CMNINFO_PHY_STATUS,\r
+ ODM_CMNINFO_MAC_STATUS,\r
+ \r
+ ODM_CMNINFO_MAX,\r
+\r
+\r
+}ODM_CMNINFO_E;\r
+\r
+typedef enum _PHYDM_API_Definition {\r
+\r
+ PHYDM_API_NBI = 1,\r
+ PHYDM_API_CSI_MASK,\r
+\r
+ \r
+} PHYDM_API_E;\r
+\r
+\r
+//\r
+// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY\r
+//\r
+typedef enum _ODM_Support_Ability_Definition\r
+{\r
+ //\r
+ // BB ODM section BIT 0-19\r
+ //\r
+ ODM_BB_DIG = BIT0,\r
+ ODM_BB_RA_MASK = BIT1,\r
+ ODM_BB_DYNAMIC_TXPWR = BIT2,\r
+ ODM_BB_FA_CNT = BIT3,\r
+ ODM_BB_RSSI_MONITOR = BIT4,\r
+ ODM_BB_CCK_PD = BIT5,\r
+ ODM_BB_ANT_DIV = BIT6,\r
+ ODM_BB_PWR_TRAIN = BIT8,\r
+ ODM_BB_RATE_ADAPTIVE = BIT9,\r
+ ODM_BB_PATH_DIV = BIT10,\r
+ ODM_BB_ADAPTIVITY = BIT13,\r
+ ODM_BB_CFO_TRACKING = BIT14,\r
+ ODM_BB_NHM_CNT = BIT15,\r
+ ODM_BB_PRIMARY_CCA = BIT16,\r
+ ODM_BB_TXBF = BIT17,\r
+ ODM_BB_DYNAMIC_ARFR = BIT18,\r
+ \r
+ //\r
+ // MAC DM section BIT 20-23\r
+ //\r
+ ODM_MAC_EDCA_TURBO = BIT20,\r
+ ODM_MAC_EARLY_MODE = BIT21,\r
+ \r
+ //\r
+ // RF ODM section BIT 24-31\r
+ //\r
+ ODM_RF_TX_PWR_TRACK = BIT24,\r
+ ODM_RF_RX_GAIN_TRACK = BIT25,\r
+ ODM_RF_CALIBRATION = BIT26,\r
+ \r
+}ODM_ABILITY_E;\r
+\r
+\r
+// ODM_CMNINFO_ONE_PATH_CCA\r
+typedef enum tag_CCA_Path\r
+{\r
+ ODM_CCA_2R = 0,\r
+ ODM_CCA_1R_A = 1,\r
+ ODM_CCA_1R_B = 2,\r
+}ODM_CCA_PATH_E;\r
+\r
+typedef enum CCA_PATHDIV_EN {\r
+ CCA_PATHDIV_DISABLE = 0,\r
+ CCA_PATHDIV_ENABLE = 1,\r
+\r
+} CCA_PATHDIV_EN_E;\r
+\r
+\r
+typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{\r
+ PHY_REG_PG_RELATIVE_VALUE = 0,\r
+ PHY_REG_PG_EXACT_VALUE = 1\r
+} PHY_REG_PG_TYPE;\r
+\r
+//\r
+// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.\r
+//\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+#if (RT_PLATFORM != PLATFORM_LINUX)\r
+typedef \r
+#endif\r
+ \r
+struct DM_Out_Source_Dynamic_Mechanism_Structure\r
+#else// for AP,ADSL,CE Team\r
+typedef struct DM_Out_Source_Dynamic_Mechanism_Structure\r
+#endif\r
+{\r
+ // Add for different team use temporarily\r
+ //\r
+ PADAPTER Adapter; // For CE/NIC team\r
+ prtl8192cd_priv priv; // For AP/ADSL team\r
+ // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.\r
+ BOOLEAN odm_ready;\r
+\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+ rtl8192cd_priv fake_priv;\r
+#endif\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
+ // ADSL_AP_BUILD_WORKAROUND\r
+ ADAPTER fake_adapter;\r
+#endif\r
+ \r
+ PHY_REG_PG_TYPE PhyRegPgValueType;\r
+ u1Byte PhyRegPgVersion;\r
+\r
+ u4Byte DebugComponents;\r
+ u4Byte DebugLevel;\r
+ \r
+ u4Byte NumQryPhyStatusAll; //CCK + OFDM\r
+ u4Byte LastNumQryPhyStatusAll; \r
+ u4Byte RxPWDBAve;\r
+ BOOLEAN MPDIG_2G; //off MPDIG\r
+ u1Byte Times_2G;\r
+ BOOLEAN bInitHwInfoByRfe;\r
+ \r
+//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
+ BOOLEAN bCckHighPower; \r
+ u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE\r
+ u1Byte ControlChannel;\r
+//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
+\r
+//--------REMOVED COMMON INFO----------//\r
+ //u1Byte PseudoMacPhyMode;\r
+ //BOOLEAN *BTCoexist;\r
+ //BOOLEAN PseudoBtCoexist;\r
+ //u1Byte OPMode;\r
+ //BOOLEAN bAPMode;\r
+ //BOOLEAN bClientMode;\r
+ //BOOLEAN bAdHocMode;\r
+ //BOOLEAN bSlaveOfDMSP;\r
+//--------REMOVED COMMON INFO----------//\r
+\r
+\r
+//1 COMMON INFORMATION\r
+\r
+ //\r
+ // Init Value\r
+ //\r
+//-----------HOOK BEFORE REG INIT-----------// \r
+ // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4\r
+ u1Byte SupportPlatform; \r
+ // ODM Platform info WIN/AP/CE = 1/2/3\r
+ u1Byte Normalrxpath;\r
+ // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K\r
+ u4Byte SupportAbility;\r
+ // ODM PCIE/USB/SDIO = 1/2/3\r
+ u1Byte SupportInterface; \r
+ // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...\r
+ u4Byte SupportICType; \r
+ // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...\r
+ u1Byte CutVersion;\r
+ // Fab Version TSMC/UMC = 0/1\r
+ u1Byte FabVersion;\r
+ // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...\r
+ u1Byte RFType;\r
+ u1Byte RFEType; \r
+ // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...\r
+ u1Byte BoardType;\r
+ u1Byte PackageType;\r
+ u2Byte TypeGLNA;\r
+ u2Byte TypeGPA;\r
+ u2Byte TypeALNA;\r
+ u2Byte TypeAPA;\r
+ // with external LNA NO/Yes = 0/1\r
+ u1Byte ExtLNA; // 2G\r
+ u1Byte ExtLNA5G; //5G\r
+ // with external PA NO/Yes = 0/1\r
+ u1Byte ExtPA; // 2G\r
+ u1Byte ExtPA5G; //5G\r
+ // with external TRSW NO/Yes = 0/1\r
+ u1Byte ExtTRSW;\r
+ u1Byte ExtLNAGain; // 2G\r
+ u1Byte PatchID; //Customer ID\r
+ BOOLEAN bInHctTest;\r
+ u1Byte WIFITest;\r
+\r
+ BOOLEAN bDualMacSmartConcurrent;\r
+ u4Byte BK_SupportAbility;\r
+ u1Byte AntDivType;\r
+ u1Byte with_extenal_ant_switch;\r
+ BOOLEAN ConfigBBRF;\r
+ u1Byte odm_Regulation2_4G;\r
+ u1Byte odm_Regulation5G;\r
+ u1Byte IQKFWOffload;\r
+ BOOLEAN cck_new_agc;\r
+//-----------HOOK BEFORE REG INIT-----------// \r
+\r
+ //\r
+ // Dynamic Value\r
+ // \r
+//--------- POINTER REFERENCE-----------//\r
+\r
+ u1Byte u1Byte_temp;\r
+ BOOLEAN BOOLEAN_temp;\r
+ PADAPTER PADAPTER_temp;\r
+ \r
+ // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2\r
+ u1Byte *pMacPhyMode;\r
+ //TX Unicast byte count\r
+ u8Byte *pNumTxBytesUnicast;\r
+ //RX Unicast byte count\r
+ u8Byte *pNumRxBytesUnicast;\r
+ // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3\r
+ u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E\r
+ // Frequence band 2.4G/5G = 0/1\r
+ u1Byte *pBandType;\r
+ // Secondary channel offset don't_care/below/above = 0/1/2\r
+ u1Byte *pSecChOffset;\r
+ // Security mode Open/WEP/AES/TKIP = 0/1/2/3\r
+ u1Byte *pSecurity;\r
+ // BW info 20M/40M/80M = 0/1/2\r
+ u1Byte *pBandWidth;\r
+ // Central channel location Ch1/Ch2/....\r
+ u1Byte *pChannel; //central channel number\r
+ BOOLEAN DPK_Done;\r
+ // Common info for 92D DMSP\r
+ \r
+ BOOLEAN *pbGetValueFromOtherMac;\r
+ PADAPTER *pBuddyAdapter;\r
+ BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave\r
+ // Common info for Status\r
+ BOOLEAN *pbScanInProcess;\r
+ BOOLEAN *pbPowerSaving;\r
+ // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.\r
+ u1Byte *pOnePathCCA;\r
+ //pMgntInfo->AntennaTest\r
+ u1Byte *pAntennaTest;\r
+ BOOLEAN *pbNet_closed;\r
+ //u1Byte *pAidMap;\r
+ u1Byte *pu1ForcedIgiLb;\r
+ BOOLEAN *pIsFcsModeEnable;\r
+/*--------- For 8723B IQK-----------*/\r
+ BOOLEAN *pIs1Antenna;\r
+ u1Byte *pRFDefaultPath;\r
+ // 0:S1, 1:S0\r
+ \r
+//--------- POINTER REFERENCE-----------//\r
+ pu2Byte pForcedDataRate;\r
+ pu1Byte HubUsbMode;\r
+ BOOLEAN *pbFwDwRsvdPageInProgress;\r
+ u4Byte *pCurrentTxTP;\r
+ u4Byte *pCurrentRxTP;\r
+ u1Byte *pSoundingSeq;\r
+//------------CALL BY VALUE-------------//\r
+ BOOLEAN bLinkInProcess;\r
+ BOOLEAN bWIFI_Direct;\r
+ BOOLEAN bWIFI_Display;\r
+ BOOLEAN bLinked;\r
+ BOOLEAN bsta_state;\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23\r
+#ifdef UNIVERSAL_REPEATER\r
+ BOOLEAN VXD_bLinked;\r
+#endif\r
+#endif // for repeater mode add by YuChen 2014.06.23 \r
+ u1Byte RSSI_Min; \r
+ u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/\r
+ BOOLEAN bIsMPChip;\r
+ BOOLEAN bOneEntryOnly;\r
+ BOOLEAN mp_mode;\r
+ u4Byte OneEntry_MACID;\r
+ u1Byte pre_number_linked_client; \r
+ u1Byte number_linked_client;\r
+ u1Byte pre_number_active_client; \r
+ u1Byte number_active_client;\r
+ // Common info for BTDM\r
+ BOOLEAN bBtEnabled; // BT is enabled\r
+ BOOLEAN bBtConnectProcess; // BT HS is under connection progress.\r
+ u1Byte btHsRssi; // BT HS mode wifi rssi value.\r
+ BOOLEAN bBtHsOperation; // BT HS mode is under progress\r
+ u1Byte btHsDigVal; // use BT rssi to decide the DIG value\r
+ BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo\r
+ BOOLEAN bBtBusy; // BT is busy.\r
+ BOOLEAN bBtLimitedDig; // BT is busy.\r
+ BOOLEAN bDisablePhyApi;\r
+//------------CALL BY VALUE-------------//\r
+ u1Byte RSSI_A;\r
+ u1Byte RSSI_B;\r
+ u1Byte RSSI_C;\r
+ u1Byte RSSI_D;\r
+ u8Byte RSSI_TRSW; \r
+ u8Byte RSSI_TRSW_H;\r
+ u8Byte RSSI_TRSW_L; \r
+ u8Byte RSSI_TRSW_iso;\r
+ u1Byte TXAntStatus;\r
+ u1Byte RXAntStatus;\r
+ u1Byte cck_lna_idx;\r
+ u1Byte cck_vga_idx;\r
+ u1Byte curr_station_id;\r
+ u1Byte ofdm_agc_idx[4];\r
+\r
+ u1Byte RxRate;\r
+ BOOLEAN bNoisyState;\r
+ u1Byte TxRate;\r
+ u1Byte LinkedInterval;\r
+ u1Byte preChannel;\r
+ u4Byte TxagcOffsetValueA;\r
+ BOOLEAN IsTxagcOffsetPositiveA;\r
+ u4Byte TxagcOffsetValueB;\r
+ BOOLEAN IsTxagcOffsetPositiveB;\r
+ u4Byte tx_tp;\r
+ u4Byte rx_tp;\r
+ u4Byte total_tp;\r
+ u8Byte curTxOkCnt;\r
+ u8Byte curRxOkCnt; \r
+ u8Byte lastTxOkCnt;\r
+ u8Byte lastRxOkCnt;\r
+ u4Byte BbSwingOffsetA;\r
+ BOOLEAN IsBbSwingOffsetPositiveA;\r
+ u4Byte BbSwingOffsetB;\r
+ BOOLEAN IsBbSwingOffsetPositiveB;\r
+ u1Byte IGI_LowerBound;\r
+ u1Byte IGI_UpperBound;\r
+ u1Byte antdiv_rssi;\r
+ u1Byte fat_comb_a;\r
+ u1Byte fat_comb_b;\r
+ u1Byte antdiv_intvl;\r
+ u1Byte AntType;\r
+ u1Byte pre_AntType;\r
+ u1Byte antdiv_period;\r
+ u1Byte evm_antdiv_period;\r
+ u1Byte antdiv_select;\r
+ u1Byte path_select; \r
+ u1Byte antdiv_evm_en;\r
+ u1Byte bdc_holdstate;\r
+ u1Byte NdpaPeriod;\r
+ BOOLEAN H2C_RARpt_connect;\r
+ BOOLEAN cck_agc_report_type;\r
+ \r
+ u1Byte dm_dig_max_TH;\r
+ u1Byte dm_dig_min_TH;\r
+ u1Byte print_agc;\r
+ u1Byte TrafficLoad;\r
+ u1Byte pre_TrafficLoad;\r
+\r
+\r
+ //For Adaptivtiy\r
+ u2Byte NHM_cnt_0;\r
+ u2Byte NHM_cnt_1;\r
+ s1Byte TH_L2H_default;\r
+ s1Byte TH_EDCCA_HL_diff_default;\r
+ s1Byte TH_L2H_ini;\r
+ s1Byte TH_EDCCA_HL_diff;\r
+ s1Byte TH_L2H_ini_mode2;\r
+ s1Byte TH_EDCCA_HL_diff_mode2;\r
+ BOOLEAN Carrier_Sense_enable;\r
+ u1Byte Adaptivity_IGI_upper;\r
+ BOOLEAN adaptivity_flag;\r
+ u1Byte DCbackoff;\r
+ BOOLEAN Adaptivity_enable;\r
+ u1Byte APTotalNum;\r
+ BOOLEAN EDCCA_enable;\r
+ ADAPTIVITY_STATISTICS Adaptivity;\r
+ //For Adaptivtiy\r
+ u1Byte LastUSBHub;\r
+ u1Byte TxBfDataRate;\r
+\r
+ u1Byte nbi_set_result;\r
+ \r
+ u1Byte c2h_cmd_start;\r
+ u1Byte fw_debug_trace[60]; \r
+ u1Byte pre_c2h_seq;\r
+ BOOLEAN fw_buff_is_enpty;\r
+ u4Byte data_frame_num;\r
+\r
+ /*for noise detection*/\r
+ BOOLEAN NoisyDecision; /*b_noisy*/\r
+ BOOLEAN pre_b_noisy; \r
+ u4Byte NoisyDecision_Smooth;\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+ ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];\r
+#endif\r
+ //\r
+ //2 Define STA info.\r
+ // _ODM_STA_INFO\r
+ // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??\r
+ PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];\r
+ u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */\r
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\r
+ s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM];\r
+#endif\r
+\r
+#if (RATE_ADAPTIVE_SUPPORT == 1)\r
+ u2Byte CurrminRptTime;\r
+ ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119\r
+#endif\r
+ //\r
+ // 2012/02/14 MH Add to share 88E ra with other SW team.\r
+ // We need to colelct all support abilit to a proper area.\r
+ //\r
+ BOOLEAN RaSupport88E;\r
+\r
+ // Define ...........\r
+\r
+ // Latest packet phy info (ODM write)\r
+ ODM_PHY_DBG_INFO_T PhyDbgInfo;\r
+ //PHY_INFO_88E PhyInfo;\r
+\r
+ // Latest packet phy info (ODM write)\r
+ ODM_MAC_INFO *pMacInfo;\r
+ //MAC_INFO_88E MacInfo;\r
+\r
+ // Different Team independt structure??\r
+\r
+ //\r
+ //TX_RTP_CMN TX_retrpo;\r
+ //TX_RTP_88E TX_retrpo;\r
+ //TX_RTP_8195 TX_retrpo;\r
+\r
+ //\r
+ //ODM Structure\r
+ //\r
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\r
+ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+ BDC_T DM_BdcTable;\r
+ #endif\r
+ \r
+ #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\r
+ SAT_T dm_sat_table;\r
+ #endif\r
+ \r
+#endif\r
+ FAT_T DM_FatTable;\r
+ DIG_T DM_DigTable;\r
+\r
+ PS_T DM_PSTable;\r
+ Pri_CCA_T DM_PriCCA;\r
+ RA_T DM_RA_Table; \r
+ FALSE_ALARM_STATISTICS FalseAlmCnt;\r
+ FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;\r
+ SWAT_T DM_SWAT_Table;\r
+ CFO_TRACKING DM_CfoTrack;\r
+ ACS DM_ACS;\r
+ CCX_INFO DM_CCX_INFO;\r
+#if (PHYDM_LA_MODE_SUPPORT == 1)\r
+ RT_ADCSMP adcsmp;\r
+#endif\r
+\r
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)\r
+ IQK_INFO IQK_info;\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+ //Path Div Struct\r
+ PATHDIV_PARA pathIQK;\r
+#endif\r
+#if(defined(CONFIG_PATH_DIVERSITY))\r
+ PATHDIV_T DM_PathDiv;\r
+#endif \r
+\r
+ EDCA_T DM_EDCA_Table;\r
+ u4Byte WMMEDCA_BE;\r
+\r
+ // Copy from SD4 structure\r
+ //\r
+ // ==================================================\r
+ //\r
+\r
+ //common\r
+ //u1Byte DM_Type; \r
+ //u1Byte PSD_Report_RXHP[80]; // Add By Gary\r
+ //u1Byte PSD_func_flag; // Add By Gary\r
+ //for DIG\r
+ //u1Byte bDMInitialGainEnable;\r
+ //u1Byte binitialized; // for dm_initial_gain_Multi_STA use.\r
+\r
+ BOOLEAN *pbDriverStopped;\r
+ BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep;\r
+ BOOLEAN *pinit_adpt_in_progress;\r
+\r
+ //PSD\r
+ BOOLEAN bUserAssignLevel;\r
+ u1Byte RSSI_BT; /*come from BT*/\r
+ BOOLEAN bPSDinProcess;\r
+ BOOLEAN bPSDactive;\r
+ BOOLEAN bDMInitialGainEnable;\r
+\r
+ //MPT DIG\r
+ RT_TIMER MPT_DIGTimer;\r
+ \r
+ //for rate adaptive, in fact, 88c/92c fw will handle this\r
+ u1Byte bUseRAMask;\r
+\r
+ ODM_RATE_ADAPTIVE RateAdaptive;\r
+ #if (defined(CONFIG_ANT_DETECTION))\r
+ ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool*/\r
+ #endif\r
+ ODM_RF_CAL_T RFCalibrateInfo;\r
+ u4Byte nIQK_Cnt;\r
+ u4Byte nIQK_OK_Cnt;\r
+ u4Byte nIQK_Fail_Cnt;\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) \r
+ //\r
+ // Power Training\r
+ //\r
+ u1Byte ForcePowerTrainingState;\r
+ BOOLEAN bChangeState;\r
+ u4Byte PT_score;\r
+ u8Byte OFDM_RX_Cnt;\r
+ u8Byte CCK_RX_Cnt;\r
+#endif\r
+ BOOLEAN bDisablePowerTraining;\r
+ u1Byte DynamicTxHighPowerLvl;\r
+ u1Byte LastDTPLvl;\r
+ u4Byte tx_agc_ofdm_18_6;\r
+ u1Byte rx_pkt_type;\r
+\r
+ //\r
+ // ODM system resource.\r
+ //\r
+\r
+ // ODM relative time.\r
+ RT_TIMER PathDivSwitchTimer;\r
+ //2011.09.27 add for Path Diversity\r
+ RT_TIMER CCKPathDiversityTimer;\r
+ RT_TIMER FastAntTrainingTimer;\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ RT_TIMER EVM_FastAntTrainingTimer;\r
+ #endif\r
+ RT_TIMER sbdcnt_timer;\r
+\r
+ // ODM relative workitem.\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+#if USE_WORKITEM\r
+ RT_WORK_ITEM PathDivSwitchWorkitem;\r
+ RT_WORK_ITEM CCKPathDiversityWorkitem;\r
+ RT_WORK_ITEM FastAntTrainingWorkitem;\r
+ RT_WORK_ITEM MPT_DIGWorkitem;\r
+ RT_WORK_ITEM RaRptWorkitem;\r
+ RT_WORK_ITEM sbdcnt_workitem;\r
+#endif\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\r
+#if (BEAMFORMING_SUPPORT == 1)\r
+ RT_BEAMFORMING_INFO BeamformingInfo;\r
+#endif \r
+#endif\r
+\r
+#ifdef CONFIG_PHYDM_DFS_MASTER\r
+ u1Byte DFS_RegionDomain;\r
+ pu1Byte dfs_master_enabled;\r
+\r
+ /*====== phydm_radar_detect_with_dbg_parm start ======*/\r
+ u1Byte radar_detect_dbg_parm_en;\r
+ u4Byte radar_detect_reg_918;\r
+ u4Byte radar_detect_reg_91c;\r
+ u4Byte radar_detect_reg_920;\r
+ u4Byte radar_detect_reg_924;\r
+ /*====== phydm_radar_detect_with_dbg_parm end ======*/\r
+#endif\r
+\r
+#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+ \r
+#if (RT_PLATFORM != PLATFORM_LINUX)\r
+} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure\r
+#else\r
+};\r
+#endif \r
+\r
+#else// for AP,ADSL,CE Team\r
+} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure\r
+#endif\r
+\r
+\r
+typedef enum _PHYDM_STRUCTURE_TYPE{\r
+ PHYDM_FALSEALMCNT,\r
+ PHYDM_CFOTRACK,\r
+ PHYDM_ADAPTIVITY,\r
+ PHYDM_ROMINFO,\r
+ \r
+}PHYDM_STRUCTURE_TYPE;\r
+\r
+\r
+\r
+ typedef enum _ODM_RF_CONTENT{\r
+ odm_radioa_txt = 0x1000,\r
+ odm_radiob_txt = 0x1001,\r
+ odm_radioc_txt = 0x1002,\r
+ odm_radiod_txt = 0x1003\r
+} ODM_RF_CONTENT;\r
+\r
+typedef enum _ODM_BB_Config_Type{\r
+ CONFIG_BB_PHY_REG, \r
+ CONFIG_BB_AGC_TAB, \r
+ CONFIG_BB_AGC_TAB_2G,\r
+ CONFIG_BB_AGC_TAB_5G, \r
+ CONFIG_BB_PHY_REG_PG,\r
+ CONFIG_BB_PHY_REG_MP,\r
+ CONFIG_BB_AGC_TAB_DIFF,\r
+} ODM_BB_Config_Type, *PODM_BB_Config_Type;\r
+\r
+typedef enum _ODM_RF_Config_Type{ \r
+ CONFIG_RF_RADIO,\r
+ CONFIG_RF_TXPWR_LMT,\r
+} ODM_RF_Config_Type, *PODM_RF_Config_Type;\r
+\r
+typedef enum _ODM_FW_Config_Type{\r
+ CONFIG_FW_NIC,\r
+ CONFIG_FW_NIC_2,\r
+ CONFIG_FW_AP,\r
+ CONFIG_FW_AP_2,\r
+ CONFIG_FW_MP,\r
+ CONFIG_FW_WoWLAN,\r
+ CONFIG_FW_WoWLAN_2,\r
+ CONFIG_FW_AP_WoWLAN,\r
+ CONFIG_FW_BT,\r
+} ODM_FW_Config_Type;\r
+\r
+// Status code\r
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\r
+typedef enum _RT_STATUS{\r
+ RT_STATUS_SUCCESS,\r
+ RT_STATUS_FAILURE,\r
+ RT_STATUS_PENDING,\r
+ RT_STATUS_RESOURCE,\r
+ RT_STATUS_INVALID_CONTEXT,\r
+ RT_STATUS_INVALID_PARAMETER,\r
+ RT_STATUS_NOT_SUPPORT,\r
+ RT_STATUS_OS_API_FAILED,\r
+}RT_STATUS,*PRT_STATUS;\r
+#endif // end of RT_STATUS definition\r
+\r
+#ifdef REMOVE_PACK\r
+#pragma pack()\r
+#endif\r
+\r
+//3===========================================================\r
+//3 AGC RX High Power Mode\r
+//3===========================================================\r
+#define LNA_Low_Gain_1 0x64\r
+#define LNA_Low_Gain_2 0x5A\r
+#define LNA_Low_Gain_3 0x58\r
+\r
+#define FA_RXHP_TH1 5000\r
+#define FA_RXHP_TH2 1500\r
+#define FA_RXHP_TH3 800\r
+#define FA_RXHP_TH4 600\r
+#define FA_RXHP_TH5 500\r
+\r
+typedef enum tag_1R_CCA_Type_Definition\r
+{\r
+ CCA_1R =0,\r
+ CCA_2R = 1,\r
+ CCA_MAX = 2,\r
+}DM_1R_CCA_E;\r
+\r
+typedef enum tag_RF_Type_Definition\r
+{\r
+ RF_Save =0,\r
+ RF_Normal = 1,\r
+ RF_MAX = 2,\r
+}DM_RF_E;\r
+\r
+//\r
+// check Sta pointer valid or not\r
+//\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
+#define IS_STA_VALID(pSta) (pSta && pSta->expire_to)\r
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+#define IS_STA_VALID(pSta) (pSta && pSta->bUsed)\r
+#else\r
+#define IS_STA_VALID(pSta) (pSta)\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP))\r
+\r
+BOOLEAN\r
+ODM_CheckPowerStatus(\r
+ IN PADAPTER Adapter\r
+ );\r
+\r
+#endif\r
+\r
+\r
+\r
+u4Byte odm_ConvertTo_dB(u4Byte Value);\r
+\r
+u4Byte odm_ConvertTo_linear(u4Byte Value);\r
+\r
+#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
+\r
+u4Byte\r
+GetPSDData(\r
+ PDM_ODM_T pDM_Odm,\r
+ unsigned int point,\r
+ u1Byte initial_gain_psd);\r
+\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) \r
+VOID\r
+ODM_DMWatchdog_LPS(\r
+ IN PDM_ODM_T pDM_Odm\r
+);\r
+#endif\r
+\r
+\r
+s4Byte\r
+ODM_PWdB_Conversion(\r
+ IN s4Byte X,\r
+ IN u4Byte TotalBit,\r
+ IN u4Byte DecimalBit\r
+ );\r
+\r
+s4Byte\r
+ODM_SignConversion(\r
+ IN s4Byte value,\r
+ IN u4Byte TotalBit\r
+ );\r
+\r
+void\r
+phydm_seq_sorting( \r
+ IN PVOID pDM_VOID,\r
+ IN OUT u4Byte *p_value,\r
+ IN OUT u4Byte *rank_idx, \r
+ IN OUT u4Byte *p_idx_out, \r
+ IN u1Byte seq_length\r
+);\r
+\r
+VOID \r
+ODM_DMInit(\r
+ IN PDM_ODM_T pDM_Odm\r
+);\r
+\r
+VOID\r
+ODM_DMReset(\r
+ IN PDM_ODM_T pDM_Odm\r
+ );\r
+\r
+VOID\r
+phydm_support_ability_debug(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte *const dm_value,\r
+ IN u4Byte *_used,\r
+ OUT char *output,\r
+ IN u4Byte *_out_len\r
+ );\r
+\r
+VOID\r
+phydm_config_trx_path(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte *const dm_value,\r
+ IN u4Byte *_used,\r
+ OUT char *output,\r
+ IN u4Byte *_out_len\r
+ );\r
+\r
+VOID\r
+ODM_DMWatchdog(\r
+ IN PDM_ODM_T pDM_Odm // For common use in the future\r
+ );\r
+\r
+VOID\r
+ODM_CmnInfoInit(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN ODM_CMNINFO_E CmnInfo,\r
+ IN u4Byte Value \r
+ );\r
+\r
+VOID\r
+ODM_CmnInfoHook(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN ODM_CMNINFO_E CmnInfo,\r
+ IN PVOID pValue \r
+ );\r
+\r
+VOID\r
+ODM_CmnInfoPtrArrayHook(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN ODM_CMNINFO_E CmnInfo,\r
+ IN u2Byte Index,\r
+ IN PVOID pValue \r
+ );\r
+\r
+VOID\r
+ODM_CmnInfoUpdate(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN u4Byte CmnInfo,\r
+ IN u8Byte Value \r
+ );\r
+\r
+#if(DM_ODM_SUPPORT_TYPE==ODM_AP)\r
+VOID \r
+ODM_InitAllThreads(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+\r
+VOID\r
+ODM_StopAllThreads(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+#endif\r
+\r
+VOID \r
+ODM_InitAllTimers(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+\r
+VOID \r
+ODM_CancelAllTimers(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+\r
+VOID\r
+ODM_ReleaseAllTimers(\r
+ IN PDM_ODM_T pDM_Odm \r
+ );\r
+\r
+\r
+\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm );\r
+VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm );\r
+\r
+\r
+\r
+u8Byte\r
+PlatformDivision64(\r
+ IN u8Byte x,\r
+ IN u8Byte y\r
+);\r
+\r
+//====================================================\r
+//3 PathDiV End\r
+//====================================================\r
+\r
+\r
+#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh\r
+\r
+typedef enum tag_DIG_Connect_Definition\r
+{\r
+ DIG_STA_DISCONNECT = 0, \r
+ DIG_STA_CONNECT = 1,\r
+ DIG_STA_BEFORE_CONNECT = 2,\r
+ DIG_MultiSTA_DISCONNECT = 3,\r
+ DIG_MultiSTA_CONNECT = 4,\r
+ DIG_CONNECT_MAX\r
+}DM_DIG_CONNECT_E;\r
+\r
+\r
+//\r
+// 2012/01/12 MH Check afapter status. Temp fix BSOD.\r
+//\r
+#define HAL_ADAPTER_STS_CHK(pDM_Odm)\\r
+ if (pDM_Odm->Adapter == NULL)\\r
+ {\\r
+ return;\\r
+ }\\r
+\r
+#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+VOID\r
+ODM_AsocEntry_Init(\r
+ IN PDM_ODM_T pDM_Odm\r
+ );\r
+\r
+\r
+PVOID\r
+PhyDM_Get_Structure(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN u1Byte Structure_Type\r
+);\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+/*===========================================================*/\r
+/* The following is for compile only*/\r
+/*===========================================================*/\r
+\r
+#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE\r
+#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE\r
+#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE\r
+#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE\r
+#define RF_T_METER_92D 0x42\r
+\r
+\r
+#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6)\r
+\r
+#define rConfig_ram64x16 0xb2c\r
+\r
+#define TARGET_CHNL_NUM_2G_5G 59\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+u1Byte GetRightChnlPlaceforIQK(u1Byte chnl);\r
+#endif\r
+\r
+//===========================================================\r
+#endif\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+void odm_dtc(PDM_ODM_T pDM_Odm);\r
+#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */\r
+\r
+\r
+VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm );\r
+\r
+\r
+#endif\r
+\r
+VOID\r
+phydm_set_ext_switch(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte *const dm_value,\r
+ IN u4Byte *_used,\r
+ OUT char *output,\r
+ IN u4Byte *_out_len \r
+);\r
+\r
+VOID\r
+phydm_api_debug(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte function_map,\r
+ IN u4Byte *const dm_value,\r
+ IN u4Byte *_used,\r
+ OUT char *output,\r
+ IN u4Byte *_out_len\r
+);\r
+\r
+u1Byte\r
+phydm_nbi_setting(\r
+ IN PVOID pDM_VOID,\r
+ IN u4Byte enable,\r
+ IN u4Byte channel,\r
+ IN u4Byte bw,\r
+ IN u4Byte f_interference,\r
+ IN u4Byte Second_ch\r
+);\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff