net: wireless: rockchip_wlan: add rtl8188fu support
[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8188fu / include / rtl8821a_xmit.h
diff --git a/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/rtl8821a_xmit.h b/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/rtl8821a_xmit.h
new file mode 100644 (file)
index 0000000..2b7320d
--- /dev/null
@@ -0,0 +1,180 @@
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2013 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __RTL8821A_XMIT_H__\r
+#define __RTL8821A_XMIT_H__\r
+\r
+#include <drv_types.h>\r
+\r
+typedef struct txdescriptor_8821a\r
+{\r
+       // Offset 0\r
+       u32 pktlen:16;\r
+       u32 offset:8;\r
+       u32 bmc:1;\r
+       u32 htc:1;\r
+       u32 rsvd0026:1;\r
+       u32 rsvd0027:1;\r
+       u32 linip:1;\r
+       u32 noacm:1;\r
+       u32 gf:1;\r
+       u32 rsvd0031:1;\r
+\r
+       // Offset 4\r
+       u32 macid:7;\r
+       u32 rsvd0407:1;\r
+       u32 qsel:5;\r
+       u32 rdg_nav_ext:1;\r
+       u32 lsig_txop_en:1;\r
+       u32 pifs:1;\r
+       u32 rate_id:5;\r
+       u32 en_desc_id:1;\r
+       u32 sectype:2;\r
+       u32 pkt_offset:5; // unit: 8 bytes\r
+       u32 moredata:1;\r
+       u32 txop_ps_cap:1;\r
+       u32 txop_ps_mode:1;\r
+\r
+       // Offset 8\r
+       u32 p_aid:9;\r
+       u32 rsvd0809:1;\r
+       u32 cca_rts:2;\r
+       u32 agg_en:1;\r
+       u32 rdg_en:1;\r
+       u32 null_0:1;\r
+       u32 null_1:1;\r
+       u32 bk:1;\r
+       u32 morefrag:1;\r
+       u32 raw:1;\r
+       u32 spe_rpt:1;\r
+       u32 ampdu_density:3;\r
+       u32 bt_null:1;\r
+       u32 g_id:6;\r
+       u32 rsvd0830:2;\r
+\r
+       // Offset 12\r
+       u32 wheader_len:4;\r
+       u32 chk_en:1;\r
+       u32 early_rate:1;\r
+       u32 hw_ssn_sel:2;\r
+       u32 userate:1;\r
+       u32 disrtsfb:1;\r
+       u32 disdatafb:1;\r
+       u32 cts2self:1;\r
+       u32 rtsen:1;\r
+       u32 hw_rts_en:1;\r
+       u32 port_id:1;\r
+       u32 navusehdr:1;\r
+       u32 use_max_len:1;\r
+       u32 max_agg_num:5;\r
+       u32 ndpa:2;\r
+       u32 ampdu_max_time:8;\r
+\r
+       // Offset 16\r
+       u32 datarate:7;\r
+       u32 try_rate:1;\r
+       u32 data_ratefb_lmt:5;\r
+       u32 rts_ratefb_lmt:4;\r
+       u32 rty_lmt_en:1;\r
+       u32 data_rt_lmt:6;\r
+       u32 rtsrate:5;\r
+       u32 pcts_en:1;\r
+       u32 pcts_mask_idx:2;\r
+\r
+       // Offset 20\r
+       u32 data_sc:4;\r
+       u32 data_short:1;\r
+       u32 data_bw:2;\r
+       u32 data_ldpc:1;\r
+       u32 data_stbc:2;\r
+       u32 vcs_stbc:2;\r
+       u32 rts_short:1;\r
+       u32 rts_sc:4;\r
+       u32 rsvd2016:7;\r
+       u32 tx_ant:4;\r
+       u32 txpwr_offset:3;\r
+       u32 rsvd2031:1;\r
+\r
+       // Offset 24\r
+       u32 sw_define:12;\r
+       u32 mbssid:4;\r
+       u32 antsel_A:3;\r
+       u32 antsel_B:3;\r
+       u32 antsel_C:3;\r
+       u32 antsel_D:3;\r
+       u32 rsvd2428:4;\r
+\r
+       // Offset 28\r
+       u32 checksum:16;\r
+       u32 rsvd2816:8;\r
+       u32 usb_txagg_num:8;\r
+\r
+       // Offset 32\r
+       u32 rts_rc:6;\r
+       u32 bar_rty_th:2;\r
+       u32 data_rc:6;\r
+       u32 rsvd3214:1;\r
+       u32 en_hwseq:1;\r
+       u32 nextneadpage:8;\r
+       u32 tailpage:8;\r
+\r
+       // Offset 36\r
+       u32 padding_len:11;\r
+       u32 txbf_path:1;\r
+       u32 seq:12;\r
+       u32 final_data_rate:8;\r
+}TXDESC_8821A, *PTXDESC_8821A;\r
+\r
+#ifdef CONFIG_SDIO_HCI\r
+s32 InitXmitPriv8821AS(PADAPTER padapter);\r
+void FreeXmitPriv8821AS(PADAPTER padapter);\r
+s32 XmitBufHandler8821AS(PADAPTER padapter);\r
+s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe);\r
+s32    HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);\r
+s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);\r
+#ifndef CONFIG_SDIO_TX_TASKLET\r
+thread_return XmitThread8821AS(thread_context context);\r
+#endif // !CONFIG_SDIO_TX_TASKLET\r
+#endif // CONFIG_SDIO_HCI\r
+\r
+#if 0\r
+#ifdef CONFIG_USB_HCI\r
+s32 rtl8821au_init_xmit_priv(PADAPTER padapter);\r
+void rtl8821au_free_xmit_priv(PADAPTER padapter);\r
+s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\r
+s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\r
+s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);\r
+s32 rtl8821au_xmit_buf_handler(PADAPTER padapter);\r
+void rtl8821au_xmit_tasklet(void *priv);\r
+s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\r
+#endif // CONFIG_USB_HCI\r
+\r
+#ifdef CONFIG_PCI_HCI\r
+s32 rtl8821e_init_xmit_priv(PADAPTER padapter);\r
+void rtl8821e_free_xmit_priv(PADAPTER padapter);\r
+struct xmit_buf* rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring);\r
+void rtl8821e_xmitframe_resume(PADAPTER padapter);\r
+s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\r
+s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\r
+void rtl8821e_xmit_tasklet(void *priv);\r
+#endif // CONFIG_PCI_HCI\r
+#endif\r
+\r
+#endif //__RTL8821_XMIT_H__\r
+\r