net: wireless: rockchip_wlan: add rtl8188fu support

[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8188fu / include / rtl8821a_spec.h

diff --git a/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/rtl8821a_spec.h b/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/rtl8821a_spec.h
new file mode 100644 (file)
index 0000000..ce0bac4
--- /dev/null
+++ b/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/rtl8821a_spec.h
@@ -0,0 +1,108 @@
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2013 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *******************************************************************************/\r
+#ifndef __RTL8821A_SPEC_H__\r
+#define __RTL8821A_SPEC_H__\r
+\r
+#include <drv_conf.h>\r
+// This file should based on "hal_com_reg.h"\r
+#include <hal_com_reg.h>\r
+// Because 8812a and 8821a is the same serial,\r
+// most of 8821a register definitions are the same as 8812a.\r
+#include <rtl8812a_spec.h>\r
+\r
+\r
+//============================================================\r
+//       8821A Regsiter offset definition\r
+//============================================================\r
+\r
+//============================================================\r
+// MAC register\r
+//============================================================\r
+\r
+//-----------------------------------------------------\r
+//     0x0000h ~ 0x00FFh       System Configuration\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+//     0x0100h ~ 0x01FFh       MACTOP General Configuration\r
+//-----------------------------------------------------\r
+#define REG_WOWLAN_WAKE_REASON          REG_MCUTST_WOWLAN\r
+\r
+//-----------------------------------------------------\r
+//     0x0200h ~ 0x027Fh       TXDMA Configuration\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+//     0x0280h ~ 0x02FFh       RXDMA Configuration\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+//     0x0300h ~ 0x03FFh       PCIe\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+//     0x0400h ~ 0x047Fh       Protocol Configuration\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+//     0x0500h ~ 0x05FFh       EDCA Configuration\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+//     0x0600h ~ 0x07FFh       WMAC Configuration\r
+//-----------------------------------------------------\r
+\r
+\r
+//============================================================\r
+// SDIO Bus Specification\r
+//============================================================\r
+\r
+//-----------------------------------------------------\r
+// SDIO CMD Address Mapping\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+// I/O bus domain (Host)\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+// SDIO register\r
+//-----------------------------------------------------\r
+#undef SDIO_REG_HCPWM1\r
+#define SDIO_REG_FREE_TXPG2            0x024\r
+#define SDIO_REG_HCPWM1                        0x025\r
+\r
+\r
+//============================================================\r
+//       Regsiter Bit and Content definition\r
+//============================================================\r
+\r
+//========================================================\r
+// General definitions\r
+//========================================================\r
+\r
+#define MACID_NUM_8821A 128\r
+#define SEC_CAM_ENT_NUM_8821A 64\r
+#define NSS_NUM_8821A 1\r
+#define BAND_CAP_8821A (BAND_CAP_2G | BAND_CAP_5G)\r
+#define BW_CAP_8821A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M)\r
+#define PROTO_CAP_8821A (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N|PROTO_CAP_11AC)\r
+\r
+#endif /* __RTL8821A_SPEC_H__ */\r
+\r