--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *******************************************************************************/\r
+#ifndef __RTL8812A_SPEC_H__\r
+#define __RTL8812A_SPEC_H__\r
+\r
+#include <drv_conf.h>\r
+\r
+\r
+//============================================================\r
+// 8812 Regsiter offset definition\r
+//============================================================\r
+\r
+//============================================================\r
+//\r
+//============================================================\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0000h ~ 0x00FFh System Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_SYS_CLKR_8812A 0x0008\r
+#define REG_AFE_PLL_CTRL_8812A 0x0028\r
+#define REG_HSIMR_8812 0x0058\r
+#define REG_HSISR_8812 0x005c\r
+#define REG_GPIO_EXT_CTRL 0x0060\r
+#define REG_GPIO_STATUS_8812 0x006C\r
+#define REG_SDIO_CTRL_8812 0x0070\r
+#define REG_OPT_CTRL_8812 0x0074\r
+#define REG_RF_B_CTRL_8812 0x0076\r
+#define REG_FW_DRV_MSG_8812 0x0088\r
+#define REG_HMEBOX_E2_E3_8812 0x008C\r
+#define REG_HIMR0_8812 0x00B0\r
+#define REG_HISR0_8812 0x00B4\r
+#define REG_HIMR1_8812 0x00B8\r
+#define REG_HISR1_8812 0x00BC\r
+#define REG_EFUSE_BURN_GNT_8812 0x00CF\r
+#define REG_SYS_CFG1_8812 0x00FC\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0100h ~ 0x01FFh MACTOP General Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_CR_8812A 0x100\r
+#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)\r
+#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)\r
+#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)\r
+#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN\r
+\r
+#define REG_RSVD3_8812 0x0168\r
+#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1\r
+#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2\r
+#define REG_C2HEVT_CMD_LEN_88XX 0x01AE\r
+\r
+#define REG_HMEBOX_EXT0_8812 0x01F0\r
+#define REG_HMEBOX_EXT1_8812 0x01F4\r
+#define REG_HMEBOX_EXT2_8812 0x01F8\r
+#define REG_HMEBOX_EXT3_8812 0x01FC\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0200h ~ 0x027Fh TXDMA Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_DWBCN0_CTRL_8812 REG_TDECTRL\r
+#define REG_DWBCN1_CTRL_8812 0x0228\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0280h ~ 0x02FFh RXDMA Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_TDECTRL_8812A 0x0208\r
+#define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/\r
+#define REG_RXDMA_PRO_8812 0x0290\r
+#define REG_EARLY_MODE_CONTROL_8812 0x02BC\r
+#define REG_RSVD5_8812 0x02F0\r
+#define REG_RSVD6_8812 0x02F4\r
+#define REG_RSVD7_8812 0x02F8\r
+#define REG_RSVD8_8812 0x02FC\r
+\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0300h ~ 0x03FFh PCIe\r
+//\r
+//-----------------------------------------------------\r
+#define REG_PCIE_CTRL_REG_8812A 0x0300\r
+#define REG_DBI_WDATA_8812 0x0348 // DBI Write Data\r
+#define REG_DBI_RDATA_8812 0x034C // DBI Read Data\r
+#define REG_DBI_ADDR_8812 0x0350 // DBI Address\r
+#define REG_DBI_FLAG_8812 0x0352 // DBI Read/Write Flag\r
+#define REG_MDIO_WDATA_8812 0x0354 // MDIO for Write PCIE PHY\r
+#define REG_MDIO_RDATA_8812 0x0356 // MDIO for Reads PCIE PHY\r
+#define REG_MDIO_CTL_8812 0x0358 // MDIO for Control \r
+#define REG_PCIE_MULTIFET_CTRL_8812 0x036A //PCIE Multi-Fethc Control\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0400h ~ 0x047Fh Protocol Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_TXPKT_EMPTY_8812A 0x041A\r
+#define REG_FWHW_TXQ_CTRL_8812A 0x0420\r
+#define REG_TXBF_CTRL_8812A 0x042C\r
+#define REG_ARFR0_8812 0x0444\r
+#define REG_ARFR1_8812 0x044C\r
+#define REG_CCK_CHECK_8812 0x0454\r
+#define REG_AMPDU_MAX_TIME_8812 0x0456\r
+#define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457\r
+\r
+#define REG_AMPDU_MAX_LENGTH_8812 0x0458\r
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D\r
+#define REG_NDPA_OPT_CTRL_8812A 0x045F\r
+#define REG_DATA_SC_8812 0x0483\r
+#ifdef CONFIG_WOWLAN\r
+#define REG_TXPKTBUF_IV_LOW 0x0484\r
+#define REG_TXPKTBUF_IV_HIGH 0x0488\r
+#endif\r
+#define REG_ARFR2_8812 0x048C\r
+#define REG_ARFR3_8812 0x0494\r
+#define REG_TXRPT_START_OFFSET 0x04AC\r
+#define REG_AMPDU_BURST_MODE_8812 0x04BC\r
+#define REG_HT_SINGLE_AMPDU_8812 0x04C7\r
+#define REG_MACID_PKT_DROP0_8812 0x04D0\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0500h ~ 0x05FFh EDCA Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_TXPAUSE_8812A 0x0522\r
+#define REG_CTWND_8812 0x0572\r
+#define REG_SECONDARY_CCA_CTRL_8812 0x0577\r
+#define REG_SCH_TXCMD_8812A 0x05F8\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0600h ~ 0x07FFh WMAC Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_MAC_CR_8812 0x0600\r
+\r
+#define REG_MAC_TX_SM_STATE_8812 0x06B4\r
+\r
+// Power\r
+#define REG_BFMER0_INFO_8812A 0x06E4\r
+#define REG_BFMER1_INFO_8812A 0x06EC\r
+#define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4\r
+#define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8\r
+#define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC\r
+\r
+// Hardware Port 2\r
+#define REG_BFMEE_SEL_8812A 0x0714\r
+#define REG_SND_PTCL_CTRL_8812A 0x0718\r
+\r
+\r
+//-----------------------------------------------------\r
+//\r
+// Redifine register definition for compatibility\r
+//\r
+//-----------------------------------------------------\r
+\r
+// TODO: use these definition when using REG_xxx naming rule.\r
+// NOTE: DO NOT Remove these definition. Use later.\r
+#define ISR_8812 REG_HISR0_8812\r
+\r
+//----------------------------------------------------------------------------\r
+// 8195 IMR/ISR bits (offset 0xB0, 8bits)\r
+//----------------------------------------------------------------------------\r
+#define IMR_DISABLED_8812 0\r
+// IMR DW0(0x00B0-00B3) Bit 0-31\r
+#define IMR_TIMER2_8812 BIT31 // Timeout interrupt 2\r
+#define IMR_TIMER1_8812 BIT30 // Timeout interrupt 1 \r
+#define IMR_PSTIMEOUT_8812 BIT29 // Power Save Time Out Interrupt\r
+#define IMR_GTINT4_8812 BIT28 // When GTIMER4 expires, this bit is set to 1 \r
+#define IMR_GTINT3_8812 BIT27 // When GTIMER3 expires, this bit is set to 1 \r
+#define IMR_TXBCN0ERR_8812 BIT26 // Transmit Beacon0 Error \r
+#define IMR_TXBCN0OK_8812 BIT25 // Transmit Beacon0 OK \r
+#define IMR_TSF_BIT32_TOGGLE_8812 BIT24 // TSF Timer BIT32 toggle indication interrupt \r
+#define IMR_BCNDMAINT0_8812 BIT20 // Beacon DMA Interrupt 0 \r
+#define IMR_BCNDERR0_8812 BIT16 // Beacon Queue DMA OK0 \r
+#define IMR_HSISR_IND_ON_INT_8812 BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)\r
+#define IMR_BCNDMAINT_E_8812 BIT14 // Beacon DMA Interrupt Extension for Win7 \r
+#define IMR_ATIMEND_8812 BIT12 // CTWidnow End or ATIM Window End\r
+#define IMR_C2HCMD_8812 BIT10 // CPU to Host Command INT Status, Write 1 clear \r
+#define IMR_CPWM2_8812 BIT9 // CPU power Mode exchange INT Status, Write 1 clear \r
+#define IMR_CPWM_8812 BIT8 // CPU power Mode exchange INT Status, Write 1 clear \r
+#define IMR_HIGHDOK_8812 BIT7 // High Queue DMA OK \r
+#define IMR_MGNTDOK_8812 BIT6 // Management Queue DMA OK \r
+#define IMR_BKDOK_8812 BIT5 // AC_BK DMA OK \r
+#define IMR_BEDOK_8812 BIT4 // AC_BE DMA OK \r
+#define IMR_VIDOK_8812 BIT3 // AC_VI DMA OK \r
+#define IMR_VODOK_8812 BIT2 // AC_VO DMA OK \r
+#define IMR_RDU_8812 BIT1 // Rx Descriptor Unavailable \r
+#define IMR_ROK_8812 BIT0 // Receive DMA OK\r
+\r
+// IMR DW1(0x00B4-00B7) Bit 0-31\r
+#define IMR_BCNDMAINT7_8812 BIT27 // Beacon DMA Interrupt 7\r
+#define IMR_BCNDMAINT6_8812 BIT26 // Beacon DMA Interrupt 6\r
+#define IMR_BCNDMAINT5_8812 BIT25 // Beacon DMA Interrupt 5\r
+#define IMR_BCNDMAINT4_8812 BIT24 // Beacon DMA Interrupt 4\r
+#define IMR_BCNDMAINT3_8812 BIT23 // Beacon DMA Interrupt 3\r
+#define IMR_BCNDMAINT2_8812 BIT22 // Beacon DMA Interrupt 2\r
+#define IMR_BCNDMAINT1_8812 BIT21 // Beacon DMA Interrupt 1\r
+#define IMR_BCNDOK7_8812 BIT20 // Beacon Queue DMA OK Interrup 7\r
+#define IMR_BCNDOK6_8812 BIT19 // Beacon Queue DMA OK Interrup 6\r
+#define IMR_BCNDOK5_8812 BIT18 // Beacon Queue DMA OK Interrup 5\r
+#define IMR_BCNDOK4_8812 BIT17 // Beacon Queue DMA OK Interrup 4\r
+#define IMR_BCNDOK3_8812 BIT16 // Beacon Queue DMA OK Interrup 3\r
+#define IMR_BCNDOK2_8812 BIT15 // Beacon Queue DMA OK Interrup 2\r
+#define IMR_BCNDOK1_8812 BIT14 // Beacon Queue DMA OK Interrup 1\r
+#define IMR_ATIMEND_E_8812 BIT13 // ATIM Window End Extension for Win7\r
+#define IMR_TXERR_8812 BIT11 // Tx Error Flag Interrupt Status, write 1 clear.\r
+#define IMR_RXERR_8812 BIT10 // Rx Error Flag INT Status, Write 1 clear\r
+#define IMR_TXFOVW_8812 BIT9 // Transmit FIFO Overflow\r
+#define IMR_RXFOVW_8812 BIT8 // Receive FIFO Overflow\r
+\r
+\r
+#ifdef CONFIG_PCI_HCI\r
+//#define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812)\r
+#define IMR_TX_MASK (IMR_VODOK_8812|IMR_VIDOK_8812|IMR_BEDOK_8812|IMR_BKDOK_8812|IMR_MGNTDOK_8812|IMR_HIGHDOK_8812)\r
+\r
+#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)\r
+\r
+#define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812|IMR_BKDOK_8812)\r
+#endif\r
+\r
+\r
+//============================================================================\r
+// Regsiter Bit and Content definition \r
+//============================================================================\r
+\r
+//2 ACMHWCTRL 0x05C0\r
+#define AcmHw_HwEn_8812 BIT(0)\r
+#define AcmHw_VoqEn_8812 BIT(1)\r
+#define AcmHw_ViqEn_8812 BIT(2)\r
+#define AcmHw_BeqEn_8812 BIT(3)\r
+#define AcmHw_VoqStatus_8812 BIT(5)\r
+#define AcmHw_ViqStatus_8812 BIT(6)\r
+#define AcmHw_BeqStatus_8812 BIT(7)\r
+\r
+//========================================================\r
+// General definitions\r
+//========================================================\r
+\r
+#define MACID_NUM_8812A 128\r
+#define SEC_CAM_ENT_NUM_8812A 64\r
+#define NSS_NUM_8812A 2\r
+#define BAND_CAP_8812A (BAND_CAP_2G | BAND_CAP_5G)\r
+#define BW_CAP_8812A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M)\r
+#define PROTO_CAP_8812A (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N|PROTO_CAP_11AC)\r
+\r
+#endif /* __RTL8812A_SPEC_H__ */\r
+\r
+#ifdef CONFIG_RTL8821A\r
+#include "rtl8821a_spec.h"\r
+#endif /* CONFIG_RTL8821A */\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff