--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *******************************************************************************/\r
+#ifndef __RTL8703B_SPEC_H__\r
+#define __RTL8703B_SPEC_H__\r
+\r
+#include <drv_conf.h>\r
+\r
+\r
+#define HAL_NAV_UPPER_UNIT_8703B 128 // micro-second\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0000h ~ 0x00FFh System Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_SYS_ISO_CTRL_8703B 0x0000 // 2 Byte\r
+#define REG_SYS_FUNC_EN_8703B 0x0002 // 2 Byte\r
+#define REG_APS_FSMCO_8703B 0x0004 // 4 Byte\r
+#define REG_SYS_CLKR_8703B 0x0008 // 2 Byte\r
+#define REG_9346CR_8703B 0x000A // 2 Byte\r
+#define REG_EE_VPD_8703B 0x000C // 2 Byte\r
+#define REG_AFE_MISC_8703B 0x0010 // 1 Byte\r
+#define REG_SPS0_CTRL_8703B 0x0011 // 7 Byte\r
+#define REG_SPS_OCP_CFG_8703B 0x0018 // 4 Byte\r
+#define REG_RSV_CTRL_8703B 0x001C // 3 Byte\r
+#define REG_RF_CTRL_8703B 0x001F // 1 Byte\r
+#define REG_LPLDO_CTRL_8703B 0x0023 // 1 Byte\r
+#define REG_AFE_XTAL_CTRL_8703B 0x0024 // 4 Byte\r
+#define REG_AFE_PLL_CTRL_8703B 0x0028 // 4 Byte\r
+#define REG_MAC_PLL_CTRL_EXT_8703B 0x002c // 4 Byte\r
+#define REG_EFUSE_CTRL_8703B 0x0030\r
+#define REG_EFUSE_TEST_8703B 0x0034\r
+#define REG_PWR_DATA_8703B 0x0038\r
+#define REG_CAL_TIMER_8703B 0x003C\r
+#define REG_ACLK_MON_8703B 0x003E\r
+#define REG_GPIO_MUXCFG_8703B 0x0040\r
+#define REG_GPIO_IO_SEL_8703B 0x0042\r
+#define REG_MAC_PINMUX_CFG_8703B 0x0043\r
+#define REG_GPIO_PIN_CTRL_8703B 0x0044\r
+#define REG_GPIO_INTM_8703B 0x0048\r
+#define REG_LEDCFG0_8703B 0x004C\r
+#define REG_LEDCFG1_8703B 0x004D\r
+#define REG_LEDCFG2_8703B 0x004E\r
+#define REG_LEDCFG3_8703B 0x004F\r
+#define REG_FSIMR_8703B 0x0050\r
+#define REG_FSISR_8703B 0x0054\r
+#define REG_HSIMR_8703B 0x0058\r
+#define REG_HSISR_8703B 0x005c\r
+#define REG_GPIO_EXT_CTRL 0x0060\r
+#define REG_PAD_CTRL1_8703B 0x0064\r
+#define REG_MULTI_FUNC_CTRL_8703B 0x0068\r
+#define REG_GPIO_STATUS_8703B 0x006C\r
+#define REG_SDIO_CTRL_8703B 0x0070\r
+#define REG_OPT_CTRL_8703B 0x0074\r
+#define REG_AFE_CTRL_4_8703B 0x0078\r
+#define REG_MCUFWDL_8703B 0x0080\r
+#define REG_HMEBOX_DBG_0_8703B 0x0088\r
+#define REG_HMEBOX_DBG_1_8703B 0x008A\r
+#define REG_HMEBOX_DBG_2_8703B 0x008C\r
+#define REG_HMEBOX_DBG_3_8703B 0x008E\r
+#define REG_HIMR0_8703B 0x00B0\r
+#define REG_HISR0_8703B 0x00B4\r
+#define REG_HIMR1_8703B 0x00B8\r
+#define REG_HISR1_8703B 0x00BC\r
+#define REG_PMC_DBG_CTRL2_8703B 0x00CC\r
+#define REG_EFUSE_BURN_GNT_8703B 0x00CF\r
+#define REG_HPON_FSM_8703B 0x00EC\r
+#define REG_SYS_CFG_8703B 0x00F0\r
+#define REG_SYS_CFG1_8703B 0x00FC\r
+#define REG_ROM_VERSION 0x00FD\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0100h ~ 0x01FFh MACTOP General Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_C2HEVT_CMD_ID_8703B 0x01A0\r
+#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1\r
+#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2\r
+#define REG_C2HEVT_CMD_LEN_8703B 0x01AE\r
+#define REG_C2HEVT_CMD_LEN_88XX REG_C2HEVT_CMD_LEN_8703B\r
+#define REG_C2HEVT_CLEAR_8703B 0x01AF\r
+#define REG_MCUTST_1_8703B 0x01C0\r
+#define REG_WOWLAN_WAKE_REASON 0x01C7\r
+#define REG_FMETHR_8703B 0x01C8\r
+#define REG_HMETFR_8703B 0x01CC\r
+#define REG_HMEBOX_0_8703B 0x01D0\r
+#define REG_HMEBOX_1_8703B 0x01D4\r
+#define REG_HMEBOX_2_8703B 0x01D8\r
+#define REG_HMEBOX_3_8703B 0x01DC\r
+#define REG_LLT_INIT_8703B 0x01E0\r
+#define REG_HMEBOX_EXT0_8703B 0x01F0\r
+#define REG_HMEBOX_EXT1_8703B 0x01F4\r
+#define REG_HMEBOX_EXT2_8703B 0x01F8\r
+#define REG_HMEBOX_EXT3_8703B 0x01FC\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0200h ~ 0x027Fh TXDMA Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_RQPN_8703B 0x0200\r
+#define REG_FIFOPAGE_8703B 0x0204\r
+#define REG_DWBCN0_CTRL_8703B REG_TDECTRL\r
+#define REG_TXDMA_OFFSET_CHK_8703B 0x020C\r
+#define REG_TXDMA_STATUS_8703B 0x0210\r
+#define REG_RQPN_NPQ_8703B 0x0214\r
+#define REG_DWBCN1_CTRL_8703B 0x0228\r
+\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0280h ~ 0x02FFh RXDMA Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_RXDMA_AGG_PG_TH_8703B 0x0280\r
+#define REG_FW_UPD_RDPTR_8703B 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1\r
+#define REG_RXDMA_CONTROL_8703B 0x0286 // Control the RX DMA.\r
+#define REG_RXPKT_NUM_8703B 0x0287 // The number of packets in RXPKTBUF. \r
+#define REG_RXDMA_STATUS_8703B 0x0288\r
+#define REG_RXDMA_MODE_CTRL_8703B 0x0290\r
+#define REG_EARLY_MODE_CONTROL_8703B 0x02BC\r
+#define REG_RSVD5_8703B 0x02F0\r
+#define REG_RSVD6_8703B 0x02F4\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0300h ~ 0x03FFh PCIe\r
+//\r
+//-----------------------------------------------------\r
+#define REG_PCIE_CTRL_REG_8703B 0x0300\r
+#define REG_INT_MIG_8703B 0x0304 // Interrupt Migration \r
+#define REG_BCNQ_DESA_8703B 0x0308 // TX Beacon Descriptor Address\r
+#define REG_HQ_DESA_8703B 0x0310 // TX High Queue Descriptor Address\r
+#define REG_MGQ_DESA_8703B 0x0318 // TX Manage Queue Descriptor Address\r
+#define REG_VOQ_DESA_8703B 0x0320 // TX VO Queue Descriptor Address\r
+#define REG_VIQ_DESA_8703B 0x0328 // TX VI Queue Descriptor Address\r
+#define REG_BEQ_DESA_8703B 0x0330 // TX BE Queue Descriptor Address\r
+#define REG_BKQ_DESA_8703B 0x0338 // TX BK Queue Descriptor Address\r
+#define REG_RX_DESA_8703B 0x0340 // RX Queue Descriptor Address\r
+#define REG_DBI_WDATA_8703B 0x0348 // DBI Write Data\r
+#define REG_DBI_RDATA_8703B 0x034C // DBI Read Data\r
+#define REG_DBI_ADDR_8703B 0x0350 // DBI Address\r
+#define REG_DBI_FLAG_8703B 0x0352 // DBI Read/Write Flag\r
+#define REG_MDIO_WDATA_8703B 0x0354 // MDIO for Write PCIE PHY\r
+#define REG_MDIO_RDATA_8703B 0x0356 // MDIO for Reads PCIE PHY\r
+#define REG_MDIO_CTL_8703B 0x0358 // MDIO for Control\r
+#define REG_DBG_SEL_8703B 0x0360 // Debug Selection Register\r
+#define REG_PCIE_HRPWM_8703B 0x0361 //PCIe RPWM\r
+#define REG_PCIE_HCPWM_8703B 0x0363 //PCIe CPWM\r
+#define REG_PCIE_MULTIFET_CTRL_8703B 0x036A //PCIE Multi-Fethc Control\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0400h ~ 0x047Fh Protocol Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_VOQ_INFORMATION_8703B 0x0400\r
+#define REG_VIQ_INFORMATION_8703B 0x0404\r
+#define REG_BEQ_INFORMATION_8703B 0x0408\r
+#define REG_BKQ_INFORMATION_8703B 0x040C\r
+#define REG_MGQ_INFORMATION_8703B 0x0410\r
+#define REG_HGQ_INFORMATION_8703B 0x0414\r
+#define REG_BCNQ_INFORMATION_8703B 0x0418\r
+#define REG_TXPKT_EMPTY_8703B 0x041A\r
+\r
+#define REG_FWHW_TXQ_CTRL_8703B 0x0420\r
+#define REG_HWSEQ_CTRL_8703B 0x0423\r
+#define REG_TXPKTBUF_BCNQ_BDNY_8703B 0x0424\r
+#define REG_TXPKTBUF_MGQ_BDNY_8703B 0x0425\r
+#define REG_LIFECTRL_CTRL_8703B 0x0426\r
+#define REG_MULTI_BCNQ_OFFSET_8703B 0x0427\r
+#define REG_SPEC_SIFS_8703B 0x0428\r
+#define REG_RL_8703B 0x042A\r
+#define REG_TXBF_CTRL_8703B 0x042C\r
+#define REG_DARFRC_8703B 0x0430\r
+#define REG_RARFRC_8703B 0x0438\r
+#define REG_RRSR_8703B 0x0440\r
+#define REG_ARFR0_8703B 0x0444\r
+#define REG_ARFR1_8703B 0x044C\r
+#define REG_CCK_CHECK_8703B 0x0454\r
+#define REG_AMPDU_MAX_TIME_8703B 0x0456\r
+#define REG_TXPKTBUF_BCNQ_BDNY1_8703B 0x0457\r
+\r
+#define REG_AMPDU_MAX_LENGTH_8703B 0x0458\r
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B 0x045D\r
+#define REG_NDPA_OPT_CTRL_8703B 0x045F\r
+#define REG_FAST_EDCA_CTRL_8703B 0x0460\r
+#define REG_RD_RESP_PKT_TH_8703B 0x0463\r
+#define REG_DATA_SC_8703B 0x0483\r
+#ifdef CONFIG_WOWLAN\r
+#define REG_TXPKTBUF_IV_LOW 0x0484\r
+#define REG_TXPKTBUF_IV_HIGH 0x0488\r
+#endif\r
+#define REG_TXRPT_START_OFFSET 0x04AC\r
+#define REG_POWER_STAGE1_8703B 0x04B4\r
+#define REG_POWER_STAGE2_8703B 0x04B8\r
+#define REG_AMPDU_BURST_MODE_8703B 0x04BC\r
+#define REG_PKT_VO_VI_LIFE_TIME_8703B 0x04C0\r
+#define REG_PKT_BE_BK_LIFE_TIME_8703B 0x04C2\r
+#define REG_STBC_SETTING_8703B 0x04C4\r
+#define REG_HT_SINGLE_AMPDU_8703B 0x04C7\r
+#define REG_PROT_MODE_CTRL_8703B 0x04C8\r
+#define REG_MAX_AGGR_NUM_8703B 0x04CA\r
+#define REG_RTS_MAX_AGGR_NUM_8703B 0x04CB\r
+#define REG_BAR_MODE_CTRL_8703B 0x04CC\r
+#define REG_RA_TRY_RATE_AGG_LMT_8703B 0x04CF\r
+#define REG_MACID_PKT_DROP0_8703B 0x04D0\r
+#define REG_MACID_PKT_SLEEP_8703B 0x04D4\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0500h ~ 0x05FFh EDCA Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_EDCA_VO_PARAM_8703B 0x0500\r
+#define REG_EDCA_VI_PARAM_8703B 0x0504\r
+#define REG_EDCA_BE_PARAM_8703B 0x0508\r
+#define REG_EDCA_BK_PARAM_8703B 0x050C\r
+#define REG_BCNTCFG_8703B 0x0510\r
+#define REG_PIFS_8703B 0x0512\r
+#define REG_RDG_PIFS_8703B 0x0513\r
+#define REG_SIFS_CTX_8703B 0x0514\r
+#define REG_SIFS_TRX_8703B 0x0516\r
+#define REG_AGGR_BREAK_TIME_8703B 0x051A\r
+#define REG_SLOT_8703B 0x051B\r
+#define REG_TX_PTCL_CTRL_8703B 0x0520\r
+#define REG_TXPAUSE_8703B 0x0522\r
+#define REG_DIS_TXREQ_CLR_8703B 0x0523\r
+#define REG_RD_CTRL_8703B 0x0524\r
+//\r
+// Format for offset 540h-542h:\r
+// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\r
+// [7:4]: Reserved.\r
+// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\r
+// [23:20]: Reserved\r
+// Description:\r
+// |\r
+// |<--Setup--|--Hold------------>|\r
+// --------------|----------------------\r
+// |\r
+// TBTT\r
+// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\r
+// Described by Designer Tim and Bruce, 2011-01-14.\r
+//\r
+#define REG_TBTT_PROHIBIT_8703B 0x0540\r
+#define REG_RD_NAV_NXT_8703B 0x0544\r
+#define REG_NAV_PROT_LEN_8703B 0x0546\r
+#define REG_BCN_CTRL_8703B 0x0550\r
+#define REG_BCN_CTRL_1_8703B 0x0551\r
+#define REG_MBID_NUM_8703B 0x0552\r
+#define REG_DUAL_TSF_RST_8703B 0x0553\r
+#define REG_BCN_INTERVAL_8703B 0x0554\r
+#define REG_DRVERLYINT_8703B 0x0558\r
+#define REG_BCNDMATIM_8703B 0x0559\r
+#define REG_ATIMWND_8703B 0x055A\r
+#define REG_USTIME_TSF_8703B 0x055C\r
+#define REG_BCN_MAX_ERR_8703B 0x055D\r
+#define REG_RXTSF_OFFSET_CCK_8703B 0x055E\r
+#define REG_RXTSF_OFFSET_OFDM_8703B 0x055F \r
+#define REG_TSFTR_8703B 0x0560\r
+#define REG_CTWND_8703B 0x0572\r
+#define REG_SECONDARY_CCA_CTRL_8703B 0x0577\r
+#define REG_PSTIMER_8703B 0x0580\r
+#define REG_TIMER0_8703B 0x0584\r
+#define REG_TIMER1_8703B 0x0588\r
+#define REG_ACMHWCTRL_8703B 0x05C0\r
+#define REG_SCH_TXCMD_8703B 0x05F8\r
+\r
+//-----------------------------------------------------\r
+//\r
+// 0x0600h ~ 0x07FFh WMAC Configuration\r
+//\r
+//-----------------------------------------------------\r
+#define REG_MAC_CR_8703B 0x0600\r
+#define REG_TCR_8703B 0x0604\r
+#define REG_RCR_8703B 0x0608\r
+#define REG_RX_PKT_LIMIT_8703B 0x060C\r
+#define REG_RX_DLK_TIME_8703B 0x060D\r
+#define REG_RX_DRVINFO_SZ_8703B 0x060F\r
+\r
+#define REG_MACID_8703B 0x0610\r
+#define REG_BSSID_8703B 0x0618\r
+#define REG_MAR_8703B 0x0620\r
+#define REG_MBIDCAMCFG_8703B 0x0628\r
+#define REG_WOWLAN_GTK_DBG1 0x630\r
+#define REG_WOWLAN_GTK_DBG2 0x634\r
+\r
+#define REG_USTIME_EDCA_8703B 0x0638\r
+#define REG_MAC_SPEC_SIFS_8703B 0x063A\r
+#define REG_RESP_SIFP_CCK_8703B 0x063C\r
+#define REG_RESP_SIFS_OFDM_8703B 0x063E\r
+#define REG_ACKTO_8703B 0x0640\r
+#define REG_CTS2TO_8703B 0x0641\r
+#define REG_EIFS_8703B 0x0642\r
+\r
+#define REG_NAV_UPPER_8703B 0x0652 // unit of 128\r
+#define REG_TRXPTCL_CTL_8703B 0x0668\r
+\r
+// Security\r
+#define REG_CAMCMD_8703B 0x0670\r
+#define REG_CAMWRITE_8703B 0x0674\r
+#define REG_CAMREAD_8703B 0x0678\r
+#define REG_CAMDBG_8703B 0x067C\r
+#define REG_SECCFG_8703B 0x0680\r
+\r
+// Power\r
+#define REG_WOW_CTRL_8703B 0x0690\r
+#define REG_PS_RX_INFO_8703B 0x0692\r
+#define REG_UAPSD_TID_8703B 0x0693\r
+#define REG_WKFMCAM_CMD_8703B 0x0698\r
+#define REG_WKFMCAM_NUM_8703B 0x0698\r
+#define REG_WKFMCAM_RWD_8703B 0x069C\r
+#define REG_RXFLTMAP0_8703B 0x06A0\r
+#define REG_RXFLTMAP1_8703B 0x06A2\r
+#define REG_RXFLTMAP2_8703B 0x06A4\r
+#define REG_BCN_PSR_RPT_8703B 0x06A8\r
+#define REG_BT_COEX_TABLE_8703B 0x06C0\r
+#define REG_BFMER0_INFO_8703B 0x06E4\r
+#define REG_BFMER1_INFO_8703B 0x06EC\r
+#define REG_CSI_RPT_PARAM_BW20_8703B 0x06F4\r
+#define REG_CSI_RPT_PARAM_BW40_8703B 0x06F8\r
+#define REG_CSI_RPT_PARAM_BW80_8703B 0x06FC\r
+\r
+// Hardware Port 2\r
+#define REG_MACID1_8703B 0x0700\r
+#define REG_BSSID1_8703B 0x0708\r
+#define REG_BFMEE_SEL_8703B 0x0714\r
+#define REG_SND_PTCL_CTRL_8703B 0x0718\r
+\r
+// LTE_COEX\r
+#define REG_LTECOEX_CTRL 0x07C0\r
+#define REG_LTECOEX_WRITE_DATA 0x07C4 \r
+#define REG_LTECOEX_READ_DATA 0x07C8\r
+#define REG_LTECOEX_PATH_CONTROL 0x70\r
+\r
+//============================================================\r
+// SDIO Bus Specification\r
+//============================================================\r
+\r
+//-----------------------------------------------------\r
+// SDIO CMD Address Mapping\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+// I/O bus domain (Host)\r
+//-----------------------------------------------------\r
+\r
+//-----------------------------------------------------\r
+// SDIO register\r
+//-----------------------------------------------------\r
+#define SDIO_REG_HCPWM1_8703B 0x025 // HCI Current Power Mode 1\r
+\r
+\r
+//============================================================================\r
+// 8703 Regsiter Bit and Content definition\r
+//============================================================================\r
+\r
+#define BIT_USB_RXDMA_AGG_EN BIT(31)\r
+#define RXDMA_AGG_MODE_EN BIT(1)\r
+\r
+#ifdef CONFIG_WOWLAN\r
+#define RXPKT_RELEASE_POLL BIT(16)\r
+#define RXDMA_IDLE BIT(17)\r
+#define RW_RELEASE_EN BIT(18)\r
+#endif\r
+\r
+//2 HSISR\r
+// interrupt mask which needs to clear\r
+#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\\r
+ HSISR_SPS_OCP_INT |\\r
+ HSISR_RON_INT |\\r
+ HSISR_PDNINT |\\r
+ HSISR_GPIO9_INT)\r
+\r
+\r
+//----------------------------------------------------------------------------\r
+// 8703B REG_CCK_CHECK (offset 0x454)\r
+//----------------------------------------------------------------------------\r
+#define BIT_BCN_PORT_SEL BIT5\r
+\r
+#ifdef CONFIG_RF_POWER_TRIM\r
+\r
+#ifdef CONFIG_RTL8703B\r
+#define EEPROM_RF_GAIN_OFFSET 0xC1\r
+#endif\r
+\r
+#define EEPROM_RF_GAIN_VAL 0x1F6\r
+#endif /*CONFIG_RF_POWER_TRIM*/\r
+\r
+\r
+//----------------------------------------------------------------------------\r
+// 8195 IMR/ISR bits (offset 0xB0, 8bits)\r
+//----------------------------------------------------------------------------\r
+#define IMR_DISABLED_8703B 0\r
+// IMR DW0(0x00B0-00B3) Bit 0-31\r
+#define IMR_TIMER2_8703B BIT31 // Timeout interrupt 2\r
+#define IMR_TIMER1_8703B BIT30 // Timeout interrupt 1 \r
+#define IMR_PSTIMEOUT_8703B BIT29 // Power Save Time Out Interrupt\r
+#define IMR_GTINT4_8703B BIT28 // When GTIMER4 expires, this bit is set to 1 \r
+#define IMR_GTINT3_8703B BIT27 // When GTIMER3 expires, this bit is set to 1 \r
+#define IMR_TXBCN0ERR_8703B BIT26 // Transmit Beacon0 Error \r
+#define IMR_TXBCN0OK_8703B BIT25 // Transmit Beacon0 OK \r
+#define IMR_TSF_BIT32_TOGGLE_8703B BIT24 // TSF Timer BIT32 toggle indication interrupt \r
+#define IMR_BCNDMAINT0_8703B BIT20 // Beacon DMA Interrupt 0 \r
+#define IMR_BCNDERR0_8703B BIT16 // Beacon Queue DMA OK0 \r
+#define IMR_HSISR_IND_ON_INT_8703B BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)\r
+#define IMR_BCNDMAINT_E_8703B BIT14 // Beacon DMA Interrupt Extension for Win7 \r
+#define IMR_ATIMEND_8703B BIT12 // CTWidnow End or ATIM Window End\r
+#define IMR_C2HCMD_8703B BIT10 // CPU to Host Command INT Status, Write 1 clear \r
+#define IMR_CPWM2_8703B BIT9 // CPU power Mode exchange INT Status, Write 1 clear \r
+#define IMR_CPWM_8703B BIT8 // CPU power Mode exchange INT Status, Write 1 clear \r
+#define IMR_HIGHDOK_8703B BIT7 // High Queue DMA OK \r
+#define IMR_MGNTDOK_8703B BIT6 // Management Queue DMA OK \r
+#define IMR_BKDOK_8703B BIT5 // AC_BK DMA OK \r
+#define IMR_BEDOK_8703B BIT4 // AC_BE DMA OK \r
+#define IMR_VIDOK_8703B BIT3 // AC_VI DMA OK \r
+#define IMR_VODOK_8703B BIT2 // AC_VO DMA OK \r
+#define IMR_RDU_8703B BIT1 // Rx Descriptor Unavailable \r
+#define IMR_ROK_8703B BIT0 // Receive DMA OK\r
+\r
+// IMR DW1(0x00B4-00B7) Bit 0-31\r
+#define IMR_BCNDMAINT7_8703B BIT27 // Beacon DMA Interrupt 7\r
+#define IMR_BCNDMAINT6_8703B BIT26 // Beacon DMA Interrupt 6\r
+#define IMR_BCNDMAINT5_8703B BIT25 // Beacon DMA Interrupt 5\r
+#define IMR_BCNDMAINT4_8703B BIT24 // Beacon DMA Interrupt 4\r
+#define IMR_BCNDMAINT3_8703B BIT23 // Beacon DMA Interrupt 3\r
+#define IMR_BCNDMAINT2_8703B BIT22 // Beacon DMA Interrupt 2\r
+#define IMR_BCNDMAINT1_8703B BIT21 // Beacon DMA Interrupt 1\r
+#define IMR_BCNDOK7_8703B BIT20 // Beacon Queue DMA OK Interrup 7\r
+#define IMR_BCNDOK6_8703B BIT19 // Beacon Queue DMA OK Interrup 6\r
+#define IMR_BCNDOK5_8703B BIT18 // Beacon Queue DMA OK Interrup 5\r
+#define IMR_BCNDOK4_8703B BIT17 // Beacon Queue DMA OK Interrup 4\r
+#define IMR_BCNDOK3_8703B BIT16 // Beacon Queue DMA OK Interrup 3\r
+#define IMR_BCNDOK2_8703B BIT15 // Beacon Queue DMA OK Interrup 2\r
+#define IMR_BCNDOK1_8703B BIT14 // Beacon Queue DMA OK Interrup 1\r
+#define IMR_ATIMEND_E_8703B BIT13 // ATIM Window End Extension for Win7\r
+#define IMR_TXERR_8703B BIT11 // Tx Error Flag Interrupt Status, write 1 clear.\r
+#define IMR_RXERR_8703B BIT10 // Rx Error Flag INT Status, Write 1 clear\r
+#define IMR_TXFOVW_8703B BIT9 // Transmit FIFO Overflow\r
+#define IMR_RXFOVW_8703B BIT8 // Receive FIFO Overflow\r
+\r
+#ifdef CONFIG_PCI_HCI\r
+//#define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B)\r
+#define IMR_TX_MASK (IMR_VODOK_8703B|IMR_VIDOK_8703B|IMR_BEDOK_8703B|IMR_BKDOK_8703B|IMR_MGNTDOK_8703B|IMR_HIGHDOK_8703B)\r
+\r
+#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)\r
+\r
+#define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B|IMR_BKDOK_8703B)\r
+#endif\r
+\r
+//========================================================\r
+// General definitions\r
+//========================================================\r
+\r
+#define MACID_NUM_8703B 16\r
+#define SEC_CAM_ENT_NUM_8703B 16\r
+#define NSS_NUM_8703B 1\r
+#define BAND_CAP_8703B (BAND_CAP_2G)\r
+#define BW_CAP_8703B (BW_CAP_20M | BW_CAP_40M)\r
+#define PROTO_CAP_8703B (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)\r
+\r
+#endif /* __RTL8703B_SPEC_H__ */\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff