net: wireless: rockchip_wlan: add rtl8188fu support

[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8188fu / include / HalPwrSeqCmd.h

diff --git a/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/HalPwrSeqCmd.h b/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/HalPwrSeqCmd.h
new file mode 100644 (file)
index 0000000..5cf122f
--- /dev/null
+++ b/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/HalPwrSeqCmd.h
@@ -0,0 +1,138 @@
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __HALPWRSEQCMD_H__\r
+#define __HALPWRSEQCMD_H__\r
+\r
+#include <drv_types.h>\r
+\r
+/*---------------------------------------------*/\r
+//3 The value of cmd: 4 bits\r
+/*---------------------------------------------*/\r
+#define PWR_CMD_READ                   0x00\r
+     // offset: the read register offset\r
+     // msk: the mask of the read value\r
+     // value: N/A, left by 0\r
+     // note: dirver shall implement this function by read & msk\r
+\r
+#define PWR_CMD_WRITE                  0x01\r
+     // offset: the read register offset\r
+     // msk: the mask of the write bits\r
+     // value: write value\r
+     // note: driver shall implement this cmd by read & msk after write\r
+\r
+#define PWR_CMD_POLLING                        0x02\r
+     // offset: the read register offset\r
+     // msk: the mask of the polled value\r
+     // value: the value to be polled, masked by the msd field.\r
+     // note: driver shall implement this cmd by\r
+     // do{\r
+     // if( (Read(offset) & msk) == (value & msk) )\r
+     // break;\r
+     // } while(not timeout);\r
+\r
+#define PWR_CMD_DELAY                  0x03\r
+     // offset: the value to delay\r
+     // msk: N/A\r
+     // value: the unit of delay, 0: us, 1: ms\r
+\r
+#define PWR_CMD_END                            0x04\r
+     // offset: N/A\r
+     // msk: N/A\r
+     // value: N/A\r
+\r
+/*---------------------------------------------*/\r
+//3 The value of base: 4 bits\r
+/*---------------------------------------------*/\r
+   // define the base address of each block\r
+#define PWR_BASEADDR_MAC               0x00\r
+#define PWR_BASEADDR_USB               0x01\r
+#define PWR_BASEADDR_PCIE              0x02\r
+#define PWR_BASEADDR_SDIO              0x03\r
+\r
+/*---------------------------------------------*/\r
+//3 The value of interface_msk: 4 bits\r
+/*---------------------------------------------*/\r
+#define        PWR_INTF_SDIO_MSK               BIT(0)\r
+#define        PWR_INTF_USB_MSK                BIT(1)\r
+#define        PWR_INTF_PCI_MSK                BIT(2)\r
+#define        PWR_INTF_ALL_MSK                (BIT(0)|BIT(1)|BIT(2)|BIT(3))\r
+\r
+/*---------------------------------------------*/\r
+//3 The value of fab_msk: 4 bits\r
+/*---------------------------------------------*/\r
+#define        PWR_FAB_TSMC_MSK                BIT(0)\r
+#define        PWR_FAB_UMC_MSK                 BIT(1)\r
+#define        PWR_FAB_ALL_MSK                 (BIT(0)|BIT(1)|BIT(2)|BIT(3))\r
+\r
+/*---------------------------------------------*/\r
+//3 The value of cut_msk: 8 bits\r
+/*---------------------------------------------*/\r
+#define        PWR_CUT_TESTCHIP_MSK    BIT(0)\r
+#define        PWR_CUT_A_MSK                   BIT(1)\r
+#define        PWR_CUT_B_MSK                   BIT(2)\r
+#define        PWR_CUT_C_MSK                   BIT(3)\r
+#define        PWR_CUT_D_MSK                   BIT(4)\r
+#define        PWR_CUT_E_MSK                   BIT(5)\r
+#define        PWR_CUT_F_MSK                   BIT(6)\r
+#define        PWR_CUT_G_MSK                   BIT(7)\r
+#define        PWR_CUT_ALL_MSK                 0xFF\r
+\r
+\r
+typedef enum _PWRSEQ_CMD_DELAY_UNIT_\r
+{\r
+       PWRSEQ_DELAY_US,\r
+       PWRSEQ_DELAY_MS,\r
+} PWRSEQ_DELAY_UNIT;\r
+\r
+typedef struct _WL_PWR_CFG_\r
+{\r
+       u16 offset;\r
+       u8 cut_msk;\r
+       u8 fab_msk:4;\r
+       u8 interface_msk:4;\r
+       u8 base:4;\r
+       u8 cmd:4;\r
+       u8 msk;\r
+       u8 value;\r
+} WLAN_PWR_CFG, *PWLAN_PWR_CFG;\r
+\r
+\r
+#define GET_PWR_CFG_OFFSET(__PWR_CMD)          __PWR_CMD.offset\r
+#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)                __PWR_CMD.cut_msk\r
+#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)                __PWR_CMD.fab_msk\r
+#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)       __PWR_CMD.interface_msk\r
+#define GET_PWR_CFG_BASE(__PWR_CMD)                    __PWR_CMD.base\r
+#define GET_PWR_CFG_CMD(__PWR_CMD)                     __PWR_CMD.cmd\r
+#define GET_PWR_CFG_MASK(__PWR_CMD)                    __PWR_CMD.msk\r
+#define GET_PWR_CFG_VALUE(__PWR_CMD)           __PWR_CMD.value\r
+\r
+\r
+//================================================================================\r
+//     Prototype of protected function.\r
+//================================================================================\r
+u8 HalPwrSeqCmdParsing(\r
+       PADAPTER                padapter,\r
+       u8                              CutVersion,\r
+       u8                              FabVersion,\r
+       u8                              InterfaceType,\r
+       WLAN_PWR_CFG    PwrCfgCmd[]);\r
+\r
+#endif\r
+\r